ON Semiconductor NB6L295M User Manual

NB6L295M

2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential CML
Outputs

Multi−Level Inputs w/ Internal Termination

The NB6L295M is a Dual Channel Programmable Delay Chip
designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295M is versatile in that two individual
variable delay channels, PD0 and PD1, can be configured in one of
two operating modes, a Dual Delay or an Extended Delay.

In the Dual Delay Mode, each channel has a programmable delay
section which is designed using a matrix of gates and a chain of
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.

The Extended Delay Mode amounts to the additive delay of PD0
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
set High. This will internally cascade the output of PD0 into the input
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
inputs, flows through PD0, cascades to the PD1 and outputs through
Q1/Q1

. There is a fixed minimum delay of 6.0 ns for the Extended

Delay Mode.

The required delay is accomplished by programming each delay
channel via a 3−pin Serial Data Interface, described in the application
section. The digitally selectable delay has an increment resolution of
typically 11 ps with a net programmable delay range of either 0 ns to
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.

The Multi−Level Inputs can be driven directly by differential
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295M 16 mA CML output contains
temperature compensation circuitry. This device is offered in a 4 mm x
4 mm 24−pin QFN Pb−free package. The NB6L295M is a member of
the ECLinPS MAX™ family of high performance products.

Features

• Input Clock Frequency > 1.5 GHz with 210 mV

V

OUTPP

• Input Data Rate > 2.5 Gb/s

• Programmable Delay Range: 0 ns to 6 ns per Delay

Channel

• Programmable Delay Range: 0 ns to 11.2 ns for

Extended Delay Mode

• Total Delay Range: 3.2 ns to 8.5 ns per Delay Channel

• Total Delay Range: 6.2 ns to 16.6 ns in Extended Delay

Mode

• Monotonic Delay: 11 ps Increments in 511 Steps

• Linearity $20 ps, Maximum

• 100 ps Typical Rise and Fall Times

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

• 2.4 ps Typical Clock Jitter, RMS

• 20 ps Pk−Pk Typical Data Dependent Jitter

• LVPECL, CML or LVDS Differential Input Compatible

• LVPECL, LVCMOS, LVTTL Single Ended Input

Compatible

• 3−Wire Serial Interface

• Input Enable/Disable

• Operating Range: V

• CML Output Level; 380 mV Peak−to−Peak, Typical

• Internal 50 W Input/Output Termination Provided

• −40°C to 85°C Ambient Operating Temperature

• 24−Pin QFN, 4 mm x 4 mm

• These are Pb−Free Devices*

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MARKING

DIAGRAM*

24

QFN−24

MN SUFFIX

24 1

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.

CASE 485L

ORDERING INFORMATION

= 2.375 V to 3.6 V

CC

1

NB6L
295M

ALYWG

G

© Semiconductor Components Industries, LLC, 2012

March, 2012 − Rev. 5

1 Publication Order Number:

NB6L295M/D

NB6L295M

Q0

Q0

0

1

0

1

1

GD*

0

1

2

GD*

0

1

4

GD*

0

1

8

GD*

Q1

0

0

0

0

Q1

1

1

GD*

1

2

GD*

1

4

GD*

1

8

GD*

PD0

0

0

1

16

GD*

0

1

32

GD*

0

1

64

GD*

0

1

128

GD*

0

1

256

GD*

9 Bit Latch

*GD = Gate Delay

PD1

1

16

GD*

0

1

32

GD*

0

1

64

GD*

0

1

128

GD*

0

1

256

GD*

0

1

9 Bit Latch

*GD = Gate Delay

PSEL

MSEL

D0

D1

D2

D3

D4

11 Bit Shift Register

D5

D6

D7

VT0

D8

50 W

IN0

IN0

50 W

VT0

VT1

50 W

IN1

IN1

50 W

VT1

SCKL

SDATA

SLOAD

Figure 1. Simplified Functional Block Diagram

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NB6L295M

Exposed Pad
(EP)

Q0

Q0

VCC0

VCC1

Q1

Q1

VCC

EN

SLOAD

SDIN

SCLK

VCC

VT0

1

2

3

4

5

6

789 1110

VT1

IN0

IN1

IN0

VT0

NB6L295M

IN1

GND

VCC0

1924 23 22 2021

18

17

16

15

14

13

12

VCC1GNDVT1

Figure 2. Pinout: QFN−24 (Top View)

Table 1. PIN DESCRIPTION

Pin Name I/O Description

1 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic
2 EN LVCMOS/LVTTL Input Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open

3 SLOAD LVCMOS/LVTTL Input Serial Load; This pin loads the configuration latches with the contents of the shift

4 SDIN LVCMOS/LVTTL Input Serial Data In; This pin acts as the data input to the serial configuration shift register.

5 SCLK LVCMOS/LVTTL Input Serial Clock In; This pin serves to clock the serial configuration shift register. Data from

6 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic
7 VT1
8 IN1 LVPECL, CML, LVDS Input Noninverted differential input. Note 1. Channel 1.

9 IN1 LVPECL, CML, LVDS Input Inverted differential input. Note 1. Channel 1.
10 VT1
11 GND Power Supply Negative Power Supply
12 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
13 Q1 CML Output
14 Q1 CML Output
15 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1
16 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
17 Q0 CML Output
18 Q0 CML Output
19 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0
20 GND Power Supply Negative Power Supply
21 VT0
22 IN0 LVPECL, CML, LVDS Input Inverted differential input. Note 1. Channel 0.
23 IN0 LVPECL, CML, LVDS Input Noninverted differential input. Note 1. Channel 0.
24 VT0

− EP Ground The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the

1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx

2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected
to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.

input then the device will be susceptible to self−oscillation.

Pin Default state LOW (37 kW Pulldown Resistor). High Forces Q LOW and Q

register. The latches will be transparent when this signal is HIGH; thus, the data must be
stable on the HIGH−to−LOW transition of S_LOAD for proper operation. Open Pin
Default state LOW (37 kW Pulldown Resistor).

Open Pin Default state LOW (37 kW Pulldown Resistor).

SDIN is sampled on the rising edge. Open Pin Default state LOW (37 kW Pulldown
Resistor).

Internal 50 W Termination Pin for IN1.

Internal 50 W Termination Pin for IN1

Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to V
Noninverted Differential Output. Channel 1. Typically terminated with 50 W resistor to V

Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to V
Noninverted Differential Output. Channel 0. Typically terminated with 50 W resistor to V

Internal 50 W Termination Pin for IN0

Internal 50 W Termination Pin for IN0

die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to GND and must be connected
to GND on the PC board.

HIGH.

CC1

CC1

CC0

CC0

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NB6L295M

Table 2. ATTRIBUTES

Characteristics Value

Input Default State Resistors

ESD Protection Human Body Model

Machine Model

Moisture Sensitivity (Note 3) QFN−24 Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 3094

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

3. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC, V
V

CC1

V

IO

V

INPP

I

IN

I

OUT

T

A

T

stg

q

JA

q

JC

T

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

,

Positive Power Supply GND = 0 V 4.0 V

CC0

Positive Input/Output Voltage GND = 0 V −0.5vVIOvVCC+0.5 4.5 V

Differential Input Voltage |INx − INx| VCC − GND V

Input Current Through R

Output Current Through R

(50 W Resistor)

T

(50 W Resistor)

T

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) (Note 4) 0 lfpm

500 lfpm

Thermal Resistance (Junction−to−Case) (Note 4) QFN−24 11 °C/W

Wave Solder Pb−Free 265 °C

QFN−24
QFN−24

37 kW

> 2 kV

> 100V

$50 mA

$50 mA

37
32

°C/W
°C/W

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NB6L295M

Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS V

CC

= V

CC0

= V

= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to

CC1

+85°C

Symbol

Characteristic Min Typ Max Unit

POWER SUPPLY CURRENT

I

CC

Power Supply Current (Inputs, VTX and Outputs Open) (Sum of ICC,
I

CC0

, and I

CC1

)

170 215 mA

CML OUTPUTS (Notes 5 and 6, Figure 22)

V

OH

V

OL

Output HIGH Voltage

Output LOW Voltage

V

= V

CC

VCC = V

VCC = V
V

= V

CC

CC0
CC0

CC0
CC0

= V
= V

= V
= V

CC1
CC1

CC1
CC1

= 3.3 V
= 2.5 V

= 3.3 V
= 2.5 V

VCC − 40

3260
2460

VCC − 500

2800
2000

VCC − 10

3290
2490

VCC − 400

2900
2100

V

CC

3300
2500

VCC − 300

3000
2200

mV

mV

DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 11 and 12) (Note 7)

V

th

V

IH

V

IL

V

ISE

Input Threshold Reference Voltage Range 1050 VCC − 150 mV

Single−Ended Input HIGH Voltage Vth +150 V

CC

mV

Single−Ended Input LOW Voltage GND Vth − 150 mV

Single−Ended Input Voltage Amplitude (VIH − VIL) 300 VCC − GND mV

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 13 and 14) (Note 8)

V

V

V

V

I

I

IHD

ILD

ID

CMR

IH

IL

Differential Input HIGH Voltage 1200 V

CC

Differential Input LOW Voltage GND VCC − 150 mV

Differential Input Voltage Swing (INx, INx) (V

IHD

− V

) 150 VCC − GND mV

ILD

Input Common Mode Range (Differential Configuration) (Note 9) 950 VCC – 75 mV

Input HIGH Current INx/INX, (VTn/VTn Open) −150 150

Input LOW Current IN/INX, (VTn/VTn Open) −150 150

mV

mA

mA

SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS

V

IH

V

IL

I

IH

I

IL

Single−Ended Input HIGH Voltage 2000 V

CC

Single−Ended Input LOW Voltage GND 800 mV

Input HIGH Current −150 150

Input LOW Current −150 150

mV

mA

mA

TERMINATION RESISTORS

R

R

TIN

TOUT

Internal Input Termination Resistor 40 50 60

Internal Output Termination Resistor 40 50 60

W

W

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

5. CML outputs loaded with 50 W to V

6. Input and output parameters vary 1:1 with V

, VIH, V

7. V

th

single−ended mode.

8. V

IHD

9. V

CMR

the differential input signal.

and V

IL,

, V

VID and V

ILD,

(min) varies 1:1 with voltage on GND pin, V

parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in

ISE

parameters must be complied with simultaneously.

CMR

for proper operation.

CC

CC

.

CMR

(max) varies 1:1 with VCC. The V

range is referenced to the most positive side of

CMR

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