ON Semiconductor NB6L295 User Manual

Page 1

NB6L295

2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs

Multi−Level Inputs w/ Internal Termination

The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de−skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two operating modes, a Dual Delay or an Extended Delay.

In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel.

The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 inputs, flows through PD0, cascades to the PD1 and outputs through Q1/Q1

. There is a fixed minimum delay of 6 ns for the Extended

Delay Mode.

The required delay is accomplished by programming each delay channel via a 3−pin Serial Data Interface, described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode.

The Multi−Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24−pin QFN Pb−free package. The NB6L295 is a member of the ECLinPS MAX™ family of high performance products.

Features

• Input Clock Frequency > 1.5 GHz with 550 mV

OUTPP

• Input Data Rate > 2.5 Gb/s

• Programmable Delay Range: 0 ns to 6 ns per Delay

Channel

• Programmable Delay Range: 0 ns to 11.2 ns for

Extended Delay Mode

• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel

• Total Delay Range: 6 ns to 17 ns in Extended Delay

Mode

• Monotonic Delay: 11 ps Increments in 511 Steps

• Linearity $20 ps, Maximum

• 100 ps Typical Rise and Fall Times

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

• 3 ps Typical Clock Jitter, RMS

• 20 ps Pk−Pk Typical Data Dependent Jitter

• LVPECL, CML or LVDS Differential Input Compatible

• LVPECL, LVCMOS, LVTTL Single−Ended Input

Compatible

• 3−Wire Serial Interface

• Input Enable/Disable

• Operating Range: V

• LVPECL Output Level; 780 mV Peak−to−Peak, Typical

• Internal 50 W Input Termination Provided

• −40°C to 85°C Ambient Operating Temperature

• 24−Pin QFN, 4 mm x 4 mm

• These are Pb−Free Devices*

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MARKING

DIAGRAM*

QFN−24

MN SUFFIX

24 1

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

CASE 485L

ORDERING INFORMATION

= 2.375 V to 3.6 V

NB6L

295

ALYWG

March, 2012 − Rev. 4

1 Publication Order Number:

NB6L295/D

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NB6L295

GD*

PD0

GD*

128

GD*

256

GD*

9 Bit Latch

*GD = Gate Delay

PD1

GD*

128

GD*

256

GD*

9 Bit Latch

PSELMSELD0D1D2D3D4D5D6D7D8

*GD = Gate Delay

11 Bit Shift Register

VT0

50 W

IN0

50 W

VT0

VT1

50 W

IN1

50 W

VT1

SCLK

SDATA

SLOAD

Figure 1. Simplified Functional Block Diagram

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NB6L295

VCC

SLOAD

IN0

VT0

IN0

VT0

GND

VCC0

1924 23 22 2021

Exposed Pad (EP)

VCC0

NB6L295

SDIN

SCLK

VCC

789 1110

VT1

IN1

VCC1GNDVT1

VCC1

Figure 2. Pinout: QFN−24 (Top View)

Table 1. PIN DESCRIPTION

Pin Name I/O Description

1 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic

2 EN LVCMOS/LVTTL Input Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default

3 SLOAD LVCMOS/LVTTL Input Serial Load; This pin loads the configuration latches with the contents of the shift register. The

4 SDIN LVCMOS/LVTTL Input Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin

5 SCLK LVCMOS/LVTTL Input Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is

6 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic

7 VT1

8 IN1 LVPECL, CML, LVDS Input Non−inverted differential input. Note 1.

9 IN1 LVPECL, CML, LVDS Input Inverted differential input. Note 1.

10 VT1

11 GND Power Supply Negative Power Supply

12 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1

13 Q1 LVPECL Output

14 Q1 LVPECL Output

15 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1

16 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0

17 Q0 LVPECL Output

18 Q0 LVPECL Output

19 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0

20 GND Power Supply Negative Power Supply

21 VT0

22 IN0 LVPECL, CML, LVDS Input Inverted differential input. Note 1.

23 IN0 LVPECL, CML, LVDS Input Noninverted differential input. Note 1.

24 VT0

− EP Ground The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for

state LOW (37 kW pulldown resistor). High forces Q LOW and Q

latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH− to−LOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown resistor).

Default state LOW (37 kW pulldown resistor).

sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor).

Internal 50 W Termination Pin for IN1

Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to

− 2.0 V.

CC1

Non−inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to

− 2.0 V.

CC1

Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to

− 2.0 V.

CC0

Non−inverted Differential Output . Channel 0. Typically terminated with 50 W resistor to

− 2.0 V.

CC0

Internal 50 W Termination Pin for IN0

improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND and must be connected to GND on the PC board.

1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and

if no signal is applied on INx/INx

input then the device will be susceptible to self−oscillation.

2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected

to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.

HIGH.

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NB6L295

Table 2. ATTRIBUTES

Characteristics Value

Input Default State Resistors

ESD Protection Human Body Model

Machine Model

Moisture Sensitivity (Note 3) QFN−24 Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 3094

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

3. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC, V V

CC1

INPP

OUT

stg

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

Positive Power Supply GND = 0 V 4.0 V

CC0

Positive Input/Output Voltage GND = 0 V −0.5 v VIO v VCC + 0.5 4.5 V

Differential Input Voltage |INx − INx| VCC − GND V

Input Current Through R

(50 W Resistor)

Output Current (LVPECL Output) Continuous

Surge

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) (Note 4)

0 lfpm 500 lfpm

QFN−24 QFN−24

Thermal Resistance (Junction−to−Case) (Note 4) QFN−24 11 °C/W

Wave Solder Pb−Free 265 °C

37 kW

> 2 kV

> 100V

$50 mA

100

37 32

mA mA

°C/W °C/W

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NB6L295

Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS V

= V

CC0

= V

= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to

CC1

+85°C

Symbol

Characteristic Min Typ Max Unit

POWER SUPPLY CURRENT

Power Supply Current (Inputs, VTx and Outputs Open) (Sum of ICC, I

CC0

, and I

CC1

)

110 140 170 mA

LVPECL OUTPUTS (Notes 5 and 6, Figure 21)

Output HIGH Voltage

Output LOW Voltage

= V

VCC = V

CC0 CC0

CC0

= V = V

= V

CC1 CC1

CC1

= 3.3 V = 2.5 V

= 3.3 V

= 2.5 V

VCC − 1075

2225 1425

VCC − 1825

1475

VCC − 1825

675

VCC − 950

2350 1550

VCC − 1725

1575

VCC − 1725

775

VCC − 825

2475 1675

VCC − 1625

1675

VCC − 1600

900

DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 10 and 11) (Note 7)

ISE

Input Threshold Reference Voltage Range 1050 VCC − 150 mV

Single−Ended Input HIGH Voltage Vth + 150 V

Single−Ended Input LOW Voltage GND Vth − 150 mV

Single−Ended Input Voltage Amplitude (VIH − VIL) 300 VCC − GND mV

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 12 and 13) (Note 8)

IHD

ILD

CMR

Differential Input HIGH Voltage 1200 V

Differential Input LOW Voltage GND VCC − 150 mV

Differential Input Voltage Swing (INx, INx) (V

IHD

− V

) 150 VCC − GND mV

ILD

Input Common Mode Range (Differential Configuration) (Note 9) 950 VCC – 75 mV

Input HIGH Current INx/INx, (VTn/VTn Open) −150 150

Input LOW Current IN/INX, (VTn/VTn Open) −150 150

SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS

Single−Ended Input HIGH Voltage 2000 V

Single−Ended Input LOW Voltage GND 800 mV

Input HIGH Current −150 150

Input LOW Current −150 150

TERMINATION RESISTORS

TIN

Internal Input Termination Resistor 40 50 60

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5. LVPECL outputs loaded with 50 W to V

6. Input and output parameters vary 1:1 with V

, VIH, V

7. V

single−ended mode.

, V

8. V

IHD

9. V

CMR

of the differential input signal.

and V

IL,,

VID and V

ILD,

(min) varies 1:1 with voltage on GND Pin, V

parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in

ISE

parameters must be complied with simultaneously.

CMR

− 2.0 V for proper operation.

(max) varies 1:1 with VCC. The V

CMR

range is referenced to the most positive side

CMR

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NB6L295

Table 5. AC CHARACTERISTICS V

Symbol

SCLK

OUTPP

DATA

Range

Serial Clock Input Frequency, 50% Duty Cycle 20 MHz

Output Voltage Amplitude (@ V (Note 15) (See Figure 22)

Maximum Data Rate (Note 14) 2.5 Gb/s Programmable Delay Range (@ 50 MHz)

Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1

Characteristic Min Typ Max Unit

INPPmin

Extended Mode IN0/IN0 to Q1/Q1

SKEW

pwmin

JITTER

Duty Cycle Skew (Note 11) Within Device Skew − Dual Mode D[8:0] = 0

Linearity (Note 12) $15 $20 ps Setup Time (@ 20 MHz) SDIN to SCLK

Hold Time SDIN to SCLK

Minimum Pulse Width SLOAD 1 ns Random Clock Jitter RMS; SETMIN to SETMAX

(Note 13) f

Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1 Extended Mode IN0/IN0 to Q1/Q1

Deterministic Jitter; SETMIN to SETMAX (Note 14)f

≤ 2.5 Gbps

Dual Mode IN0/IN0 to Q0/Q0 or IN1/IN1 to Q1/Q1

INPP

Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15)

Output Rise/Fall Times (@ 50 MHz), (20% − 80%) Qx,

Symbol Characteristic

PLH PHL

Propagation Delay (@ 50 MHz)

Dual Mode IN0/IN0

to Q0/Q0 or IN1/IN1 to Q1/Q1

= V

CC0

) fin ≤ 1.5 GHz

SLOAD to SCLK

= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 10)

CC1

530 780 mV

0 0

5.7

11.2

0 2

D[8:0] = 1

to SDIN

0.5

1.5

0.5

1.0

0.3

1.0

0.6 ns

1.0

to SLOAD

≤ 1.5 GHz

DAT

0.5

3 6

150 VCC − GND mV

85 120 170 ps

−405C +255C +855C

Min Typ Max Min Ty p Max Min Typ Max

D[8:0] = 0 D[8:0] = 1

2.7

7.2

2.9

8.0

3.2

8.8

2.8

7.5

3.1

8.4

3.4

9.3

2.9

7.9

6.9

13.7

100 175

10 20

3.2

9.2

Unit

3.6

9.9

Extended Mode IIN0/IN0 to Q1/Q1

5.0

5.5

6.0

5.2

5.8

6.3

5.5

6.2

D[8:0] = 0

14.2

15.2

17.1

14.8

16.5

18.2

D[8:0] = 1

Step Delay

15.6

16.4

6.8

19.6

(Selected D Bit HIGH All Others LOW)

D0 HIGH D1 HIGH D2 HIGH D3 HIGH D4 HIGH D5 HIGH D6 HIGH D7 HIGH D8 HIGH

9.6

19.4 40 81

167 338

678 1358 2715

8.7 19 42 85

175 355

714 1432 2861

24.4 52 99

196 389

774 1544 3074

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

10.Measured by forcing V = 50 W to VCC. See Figure 20. Input edge rates 40 ps (20% − 80%).

11.Duty cycle skew is measured between differential outputs using the deviations of the sum of T

12.Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps.

INPPmin

and V

from a 50% duty cycle clock source, V

INPPmax

(min and max). All loading with an external

CMR

− and Tpw+ @ 0.5 GHz.

13.Additive random CLOCK jitter with 50% duty cycle input clock signal.

14.NRZ data at PRBS23 and K28.5.

15.Input and output voltage swing is a single−ended measurement operating in differential mode.

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NB6L295

Serial Data Interface Programming

The NB6L295 is programmed by loading the 11−Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11−bit load cycle is required to program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5 and 6.

DUAL MODE OPERATIONS

Control

PD0 Programmable Delay

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 1

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

(MSB) (LSB)

Bits

PD1 Programmable Delay

Value

Bit Name

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

(MSB) (LSB)

Figure 3. PDO Shift Register Figure 4. PD1 Shift Register

EXTENDED MODE OPERATIONS

Control

PD0 Programmable Delay

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

(MSB) (LSB)

Bits

PD1 Programmable Delay

Value

Bit Name

D8 D7 D6 D5 D4 D3 D2 D1 D0 MSEL PSEL

(MSB) (LSB)

Figure 5. PDO Shift Register Figure 6. PD1 Shift Register

Refer to Table 6, Channel and Mode Select BIT Functions. In a load cycle, the 11−Bit Shift Register least significant bit (clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and the device uses both channels independently. A pulse edge entering IN0/IN0 from Q0/Q0

. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.

is delayed according to the values in PD0 and exits

When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 through PD0 and is extended through PD1 to exit at Q1 and Q1

. The most significant 9−bits, D[8:0] are delay value data for

both channels. See Figure 7.

Control

Bits

Value

Bit Name

Control

Bits

Value

Bit Name

and flows

Table 6. CHANNEL AND MODE SELECT BIT FUNCTIONS

BIT Name Function

PSEL

MSEL

D[8:0] Select one of 512 Delay Values

0 Loads Data to PD0

1 Loads Data to PD1

0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path

1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs, Q0−LOW, Q0

−HIGH.

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NB6L295

SLOAD

Q0/Q0

PD0 Delay PD1 Delay

MSEL

D8D7D6D5D4D3D2D1D0

SDATA

SCLK

D8D7D6D5D4D3D2D1D0

11−Bit Shift Register

D8D7D6D5D4D3D2D1D0

MSEL

PSEL

Q1/Q1

PD1 LatchPD0 Latch

Figure 7. Serial Data Interface, Shift Register, Data Latch, Programmable Delay Channels

Serial Data Interface Loading

Loading the device through the 3 input Serial Data Interface (SDI) is accomplished by sending data into the SDIN pin by using the SCLK input pin and latching the data with the SLOAD input pin. The 11−bit SHIFT REGISTER shifts once per rising edge of the SCLK input. The serial input SDIN must meet setup and hold timing as specified in the AC Characteristics section of this document for each bit and clock pulse. The SLOAD line loads the value of the shift register on a LOW−to−HIGH edge transition (transparent state) into a data Latch register and latches the data with a subsequent HIGH−to−LOW edge transition. Further changes in SDIN or SCLK are not recognized by the latched register. The internal multiplexer states are set by the PSEL and MSEL bits in the SHIFT register. Figure 6 shows the timing diagram of a typical load sequence.

Input EN programming, the EN

The disabling of EN

should be LOW (enabled) prior to SDI programming, then pulled HIGH (disabled) during programming. After

should be returned LOW (enabled) for functional delay operation.

(HIGH) forces Qx LOW and Qx HIGH and is included during programming to prevent (or mask out) any potential runt pulses or extended pulses which might occur in the internal delay gates programming switching, but it is not required for programming.

LSB

PSEL MSEL D0 D1 D2 D3 D4 D5 D6 D7 D8

SDIN

MSB

SCLK

SLOAD ts SDIN to

SCLK

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10

SCLK to SLOAD

SDIN to SCLK

Figure 8. SDI Timing Diagram

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NB6L295

Table 7 shows theoretical values of delay capabilities in both the Dual Delay Mode and in the Extended Delay Modes of operation.

Table 7. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN DUAL MODE

INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1

Dual Mode

PD1 D[8:0] (Decimal) PD0 D[8:0] (Decimal) MSEL

000000000 (0) 000000000 (0) 0 0 0

000000000 (0) 000000001 (1) 0 11 0

000000000 (0) 000000010 (2) 0 22 0

000000000 (0) 000000011 (3) 0 33 0

000000000 (0) 000000100 (4) 0 44 0

000000000 (0) 000000101 (5) 0 55 0

000000000 (0) 000000110 (6) 0 66 0

000000000 (0) 000000111 (7) 0 77 0

000000000 (0) 000001000 (8) 0 88 0

•

000000000 (0) 000010000 (16) 0 176 0

000000000 (0) 000100000 (32) 0 352 0

000000000 (0) 001000000 (64) 0 704 0

000000000 (0) 111111101 (509) 0 5599 0

000000000 (0) 111111110 (510) 0 5610 0

000000000 (0) 111111111 (511) 0 5621 0

*Fixed minimum delay not included

Table 8. EXAMPLES OF THEORETICAL DELAY VALUES FOR PD0 AND PD1 IN EXTENDED MODE

INPUTS: IN0/IN0, IN1/IN1, OUTPUTS: Q0/Q0, Q1, Q1

Extended Delay Mode

PD1 D[8:0]

000000000 (0) 000000000 (0) 1 0 0 0

000000000 (0) 000000001 (1) 1 0 11 11

000000000 (0) 000000010 (2) 1 0 22 22

000000000 (0) 000000011 (3) 1 0 33 33

000000000 (0) 111111101 (509) 1 0 5599 5599

000000000 (0) 111111110 (510) 1 0 5610 5610

000000000 (0) 111111111 (511) 1 0 5621 5621

000000001 (1) 111111111 (511) 1 11 5621 5632

000000010 (2) 111111111 (511) 1 22 5621 5643

11111110 0 (508) 111111111 (511) 1 5588 5621 11209

11111110 1 (509) 111111111 (511) 1 5599 5621 11220

111111110 (510) 111111111 (511) 1 5610 5621 11231

111111111 (511) 111111111 (511) 1 5621 5621 11242

*Fixed minimum delay not included

(Decimal)

PD0 D[8:0]

•

(Decimal)

MSEL

PD0 Delay* (ps) PD1 Delay* (ps)

•

PD0* (ps) PD1* (ps) Total Delay* (ps)

•

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NB6L295

INx

Figure 10. Differential Input Driven

Single−Ended

INx

VTx

50 W

INx

50 W

VTx

Figure 9. Input Structure

thmax

thmin

GND

IHmax

ILmax

IHmin

ILmin

Figure 11. Vth Diagram

GND

INx

Figure 12. Differential Inputs

Driven Differentially

CMR

Figure 14. V

Diagram Figure 15. AC Reference Measurement

CMR

IHD(MAX)

ILD(MAX)

IHD

VID = V

ILD

IHD(MIN)

ILD(MIN)

IHD

− V

ILD

INx

VID = |V

IHD

ILD

IHD(INx)

− V

ILD(INx)|

Figure 13. Differential Inputs Driven

Differentially

= VIH(INx) − VIL(INx)

INPP

= VOH(Qx) − VOL(Qx)

OUTPP

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NB6L295

Zo = 50 W

LVPECL

Driver

VTx VTx

Zo = 50 W

VTx = VTx = VCC − 2.0 V

GND

Figure 16. LVPECL Interface

INx

NB6L295

50 W

GND

CML

Driver

Zo = 50 W

VTx

INx

LVDS Driver

NB6L295

50 W*

INx

Zo = 50 W

VTx VTx

Zo = 50 W

x = VTx

INx

Figure 17. LVDS Interface

NB6L295

50 W*

GNDGND

Differential

Driver

GND

Zo = 50 W

VTx

REFAC

VTx

Zo = 50 W

x = VTx = External V

Zo = 50 W

INx

x = VTx = V

GND

Figure 18. CML Interface, Standard 50 W Load

INx

NB6L295

50 W*

REFAC

GND

Single−Ended

Driver

GND

Zo = 50 W

VTx

REFAC

VTx

x = VTx = External V

INx

REFAC

NB6L295

50 W*

GND

Figure 19. Capacitor−Coupled Differential

Interface (V V

REFAC

x/VTx Connected to V

REFAC

Bypassed to Ground with 0.1 mF

Capacitor)

;

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Figure 20. Capacitor−Coupled Single−Ended

Interface (V

REFAC

x/VTx Connected to External V

Bypassed to Ground with 0.1 mF Capacitor)

REFAC

;

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NB6L295

Z = 50 W

Driver Device

Z = 50 W

Q D

50 W50 W

− 2.0 V

TT =

Figure 21. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

800

700

600

500

400

Receiver Device

300

AMPLITUDE (mV)

200

, TYPICAL OUTPUT VOLTAGE

100

OUTPP

, CLOCK OUTPUT FREQUENCY (GHz)

OUT

Figure 22. Output Voltage Amplitude (V

1.51.00.50

OUTPP

2.0

) vs.

Output Frequency at Ambient Temperature (Typical)

ORDERING INFORMATION

Device Package Shipping

NB6L295MNG QFN−24

92 Units / Rail

(Pb−free)

NB6L295MNTXG QFN−24

3000 / Tape & Reel

(Pb−free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†

ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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Page 13

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

PIN 1

REFEENCE

0.15 C

TOP VIEW

DETAIL B

0.10 C

0.08 C

NOTE 4

DETAIL A

SIDE VIEW

e/2

BOTTOM VIEW

RECOMMENDED

SOLDERING FOOTPRINT

4.30

2.90

A B

SEATING

24X

PLANE

24X

0.10 B

0.05

0.55

24X

NOTE 3

QFN24, 4x4, 0.5P

CASE 485L

ISSUE B

DETAIL A

ALTERNATE

CONSTRUCTIONS

MOLD CMPDEXPOSED Cu

DETAIL B

ALTERNATE TERMINAL

CONSTRUCTIONS

DATE 05 JUN 2012

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF

b 0.20 0.30

D 4.00 BSC D2 2.70 2.90

E 4.00 BSC E2 2.70 2.90

e 0.50 BSC

L 0.30 0.50 L1 0.05 0.15

GENERIC

MARKING DIAGRAM*

XXXXX XXXXX ALYWG

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

24X

0.32

4.30

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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2.90

0.50

PITCH

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

DIMENSIONS: MILLIMETERS

98AON11783D

QFN24, 4X4, 0.5P

Page 14

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