ON Semiconductor NB6L295 User Manual

NB6L295

2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential LVPECL Outputs

Multi−Level Inputs w/ Internal Termination

The NB6L295 is a Dual Channel Programmable Delay Chip designed primarily for Clock or Data de−skewing and timing adjustment. The NB6L295 is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of two operating modes, a Dual Delay or an Extended Delay.

In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel.

The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the IN0/IN0 inputs, flows through PD0, cascades to the PD1 and outputs through Q1/Q1

. There is a fixed minimum delay of 6 ns for the Extended

Delay Mode.

The required delay is accomplished by programming each delay channel via a 3−pin Serial Data Interface, described in the application section. The digitally selectable delay has an increment resolution of typically 11 ps with a net programmable delay range of either 0 ns to 6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the Extended Delay Mode.

The Multi−Level Inputs can be driven directly by differential LVPECL, LVDS or CML logic levels; or by single ended LVPECL, LVCMOS or LVTTL. A single enable pin is available to control both inputs. The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered in a 4 mm x 4 mm 24−pin QFN Pb−free package. The NB6L295 is a member of the ECLinPS MAX™ family of high performance products.

Features

• Input Clock Frequency > 1.5 GHz with 550 mV

OUTPP

• Input Data Rate > 2.5 Gb/s

• Programmable Delay Range: 0 ns to 6 ns per Delay

Channel

• Programmable Delay Range: 0 ns to 11.2 ns for

Extended Delay Mode

• Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel

• Total Delay Range: 6 ns to 17 ns in Extended Delay

Mode

• Monotonic Delay: 11 ps Increments in 511 Steps

• Linearity $20 ps, Maximum

• 100 ps Typical Rise and Fall Times

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

• 3 ps Typical Clock Jitter, RMS

• 20 ps Pk−Pk Typical Data Dependent Jitter

• LVPECL, CML or LVDS Differential Input Compatible

• LVPECL, LVCMOS, LVTTL Single−Ended Input

Compatible

• 3−Wire Serial Interface

• Input Enable/Disable

• Operating Range: V

• LVPECL Output Level; 780 mV Peak−to−Peak, Typical

• Internal 50 W Input Termination Provided

• −40°C to 85°C Ambient Operating Temperature

• 24−Pin QFN, 4 mm x 4 mm

• These are Pb−Free Devices*

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MARKING

DIAGRAM*

QFN−24

MN SUFFIX

24 1

A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet.

CASE 485L

ORDERING INFORMATION

= 2.375 V to 3.6 V

NB6L

295

ALYWG

March, 2012 − Rev. 4

1 Publication Order Number:

NB6L295/D

NB6L295

GD*

PD0

GD*

128

GD*

256

GD*

9 Bit Latch

*GD = Gate Delay

PD1

GD*

128

GD*

256

GD*

9 Bit Latch

PSELMSELD0D1D2D3D4D5D6D7D8

*GD = Gate Delay

11 Bit Shift Register

VT0

50 W

IN0

50 W

VT0

VT1

50 W

IN1

50 W

VT1

SCLK

SDATA

SLOAD

Figure 1. Simplified Functional Block Diagram

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NB6L295

VCC

SLOAD

IN0

VT0

IN0

VT0

GND

VCC0

1924 23 22 2021

Exposed Pad (EP)

VCC0

NB6L295

SDIN

SCLK

VCC

789 1110

VT1

IN1

VCC1GNDVT1

VCC1

Figure 2. Pinout: QFN−24 (Top View)

Table 1. PIN DESCRIPTION

Pin Name I/O Description

1 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic

2 EN LVCMOS/LVTTL Input Input Enable/ Disable for both PD0 and PD1. LOW for enable, HIGH for disable, Open Pin Default

3 SLOAD LVCMOS/LVTTL Input Serial Load; This pin loads the configuration latches with the contents of the shift register. The

4 SDIN LVCMOS/LVTTL Input Serial Data In; This pin acts as the data input to the serial configuration shift register. Open Pin

5 SCLK LVCMOS/LVTTL Input Serial Clock In; This pin serves to clock the serial configuration shift register. Data from SDIN is

6 VCC Power Supply Positive Supply Voltage for the Inputs and Core Logic

7 VT1

8 IN1 LVPECL, CML, LVDS Input Non−inverted differential input. Note 1.

9 IN1 LVPECL, CML, LVDS Input Inverted differential input. Note 1.

10 VT1

11 GND Power Supply Negative Power Supply

12 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1

13 Q1 LVPECL Output

14 Q1 LVPECL Output

15 VCC1 Power Supply Positive Supply Voltage for the Q1/Q1 outputs, channel PD1

16 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0

17 Q0 LVPECL Output

18 Q0 LVPECL Output

19 VCC0 Power Supply Positive Supply Voltage for the Q0/Q0 outputs, channel PD0

20 GND Power Supply Negative Power Supply

21 VT0

22 IN0 LVPECL, CML, LVDS Input Inverted differential input. Note 1.

23 IN0 LVPECL, CML, LVDS Input Noninverted differential input. Note 1.

24 VT0

− EP Ground The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to the die for

state LOW (37 kW pulldown resistor). High forces Q LOW and Q

latches will be transparent when this signal is HIGH; thus, the data must be stable on the HIGH− to−LOW transition of S_LOAD for proper operation. Open Pin Default state LOW (37 kW pulldown resistor).

Default state LOW (37 kW pulldown resistor).

sampled on the rising edge. Open Pin Default state LOW (37 kW pulldown resistor).

Internal 50 W Termination Pin for IN1

Inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to

− 2.0 V.

CC1

Non−inverted Differential Output. Channel 1. Typically terminated with 50 W resistor to

− 2.0 V.

CC1

Inverted Differential Output. Channel 0. Typically terminated with 50 W resistor to

− 2.0 V.

CC0

Non−inverted Differential Output . Channel 0. Typically terminated with 50 W resistor to

− 2.0 V.

CC0

Internal 50 W Termination Pin for IN0

improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND and must be connected to GND on the PC board.

1. In the differential configuration when the input termination pin (VTx/VTx) are connected to a common termination voltage or left open, and

if no signal is applied on INx/INx

input then the device will be susceptible to self−oscillation.

2. All VCC, VCC0 and VCC1 Pins must be externally connected to the same power supply for proper operation. Both VCC0s are connected

to each other and both VCC1s are connected to each other: VCC0 and VCC1 are separate.

HIGH.

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NB6L295

Table 2. ATTRIBUTES

Characteristics Value

Input Default State Resistors

ESD Protection Human Body Model

Machine Model

Moisture Sensitivity (Note 3) QFN−24 Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 3094

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

3. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC, V V

CC1

INPP

OUT

stg

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

Positive Power Supply GND = 0 V 4.0 V

CC0

Positive Input/Output Voltage GND = 0 V −0.5 v VIO v VCC + 0.5 4.5 V

Differential Input Voltage |INx − INx| VCC − GND V

Input Current Through R

(50 W Resistor)

Output Current (LVPECL Output) Continuous

Surge

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) (Note 4)

0 lfpm 500 lfpm

QFN−24 QFN−24

Thermal Resistance (Junction−to−Case) (Note 4) QFN−24 11 °C/W

Wave Solder Pb−Free 265 °C

37 kW

> 2 kV

> 100V

$50 mA

100

37 32

mA mA

°C/W °C/W

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NB6L295

Table 4. DC CHARACTERISTICS, MULTI−LEVEL INPUTS V

= V

CC0

= V

= 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to

CC1

+85°C

Symbol

Characteristic Min Typ Max Unit

POWER SUPPLY CURRENT

Power Supply Current (Inputs, VTx and Outputs Open) (Sum of ICC, I

CC0

, and I

CC1

)

110 140 170 mA

LVPECL OUTPUTS (Notes 5 and 6, Figure 21)

Output HIGH Voltage

Output LOW Voltage

= V

VCC = V

CC0 CC0

CC0

= V = V

= V

CC1 CC1

CC1

= 3.3 V = 2.5 V

= 3.3 V

= 2.5 V

VCC − 1075

2225 1425

VCC − 1825

1475

VCC − 1825

675

VCC − 950

2350 1550

VCC − 1725

1575

VCC − 1725

775

VCC − 825

2475 1675

VCC − 1625

1675

VCC − 1600

900

DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 10 and 11) (Note 7)

ISE

Input Threshold Reference Voltage Range 1050 VCC − 150 mV

Single−Ended Input HIGH Voltage Vth + 150 V

Single−Ended Input LOW Voltage GND Vth − 150 mV

Single−Ended Input Voltage Amplitude (VIH − VIL) 300 VCC − GND mV

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 12 and 13) (Note 8)

IHD

ILD

CMR

Differential Input HIGH Voltage 1200 V

Differential Input LOW Voltage GND VCC − 150 mV

Differential Input Voltage Swing (INx, INx) (V

IHD

− V

) 150 VCC − GND mV

ILD

Input Common Mode Range (Differential Configuration) (Note 9) 950 VCC – 75 mV

Input HIGH Current INx/INx, (VTn/VTn Open) −150 150

Input LOW Current IN/INX, (VTn/VTn Open) −150 150

SINGLE−ENDED LVCMOS/LVTTL CONTROL INPUTS

Single−Ended Input HIGH Voltage 2000 V

Single−Ended Input LOW Voltage GND 800 mV

Input HIGH Current −150 150

Input LOW Current −150 150

TERMINATION RESISTORS

TIN

Internal Input Termination Resistor 40 50 60

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5. LVPECL outputs loaded with 50 W to V

6. Input and output parameters vary 1:1 with V

, VIH, V

7. V

single−ended mode.

, V

8. V

IHD

9. V

CMR

of the differential input signal.

and V

IL,,

VID and V

ILD,

(min) varies 1:1 with voltage on GND Pin, V

parameters must be complied with simultaneously. Vth is applied to the complementary input when operating in

ISE

parameters must be complied with simultaneously.

CMR

− 2.0 V for proper operation.

(max) varies 1:1 with VCC. The V

CMR

range is referenced to the most positive side

CMR

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