ON Semiconductor NB4N441 User Manual

NB4N441

3.3V Serial Input
MultiProtocol PLL Clock
Synthesizer, Differential
LVPECL Output

Description

The NB4N441 is a precision clock synthesizer which generates a
differential LVPECL clock output frequency from 12.5 MHz to
425 MHz. A Serial Peripheral Interface (SPI) is used to configure the
device to produce one of sixteen popular standard protocol output
frequencies from a single 27 MHz crystal reference. The NB4N441
also has the added feature of allowing application specific output
frequencies from 12.5 MHz to 425 MHz using crystals within the
range of 10 MHz to 28 MHz.

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QFN−24
MN SUFFIX
CASE 485L

MARKING

DIAGRAM*

24

NB4N

441

ALYWG

G

Features

• Performs Precision Clock Generation and Synthesis from a Single

27 MHz Crystal Reference

• Serial Load Capability for Proprietary Frequencies

• Flexible Input Allows for External Clock Reference

• Exceeds Bellcore and ITU Jitter Generation Specification

• PLL Lock Detect Output

• Output Enable

• Fully Integrated Phase−Lock−Loop with Internal Loop Filter

• Operating Range: V

= 3.135 V to 3.465 V

CC

• Small Footprint 24 Pin QFN

• These are Pb−Free Devices*

LOCKED

27 MHz

XTAL

OSC

B

R

FB

Feedback

Divider

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.

OUTDIV

B2, 4, 8,

16, 32

CLKOUT

CLKOUT

OE

VCC − 2 V

SDATA

SCLOCK

SLOAD

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2011

April, 2011 − Rev. 2

Frequency Control Logic

Serial Load

Figure 1. Simplified Block Diagram

1 Publication Order Number:

NB4N441/D

NB4N441

CLK/XTAL1

XTAL2

SDATA

SCLOCK

SLOAD

V

CC

XTAL

OSC

GND

Input

Prescaler

PB

LOCKED

PFD

VCC_PLL

Loop
Filter

R

FB

Feedback

Divider (MB)

P[4:0] M[9:0] N[3:0]

Frequency Control Logic

Serial Load

Figure 2. Block Diagram

CC

V

CLKOUT

CLKOUT

OE

VCO

LOCKED

GND

1924 23 22 2021

OUTDIV (NB)

B2, 4, 8,

16, 32

Exposed Pad
(EP)

OE

CLKOUT
CLKOUT

GND

NC

VCC_PLL

NC

NC

GND

1

2

3

4

5

6

789 1110

XTAL2

GND

NC

CC

V

18

17

16

15

14

13

12

CC

V

CLK/XTAL1

Figure 3. QFN−24 Lead Pinout (Top View)

GND

SCLOCK

SDATA

SLOAD

NC

V

CC

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NB4N441

Table 1. PIN DESCRIPTION

Pin Name I/O Description

11, 12, 13, 24 V

3 VCC_PLL PLL Power Supply Positive supply voltage for the PLL.

1, 6, 9, 18, 19 GND Ground Ground.

20 LOCKED LVTTL Lock Output When Low, this output provides indication that the PLL is

2, 4, 5, 10, 14 NC No Connect.

8 CLK / XTAL1,

7 XTAL2

15 SLOAD** LVTTL / LVCMOS,

16 SDATA** LVTTL / LVCMOS

17 SCLOCK** LVTTL / LVCMOS

21 OE* LVTTL Input Synchronous Output Enable. When OE is HIGH or left

22, 23 CLKOUT

*Pins will default HIGH when left Open
**Pins will default LOW when left Open

CC

CLKOUT

EP The Exposed Pad on the 24 pin QFN package bottom is

Power Supply Positive supply voltage.

locked and the device is in proper operating mode. When
High, the PLL is out of lock.

LVTTL/LVCMOS Single Ended

Clock or XTAL Inputs

Serial Load Input

Serial Data Input

Serial Clock Input

LVPECL Output Differential LVPECL Clock Outputs, Typically terminated with

The crystal is connected between the XTAL1 and XTAL2 pin.
If driving single−ended, use XTAL1 and leave XTAL2
floating.

Serial Load.

Serial Data Input.

Serial Clock Input.

OPEN, the outputs are enabled. When OE is LOW, the
outputs are disabled.

50 W resistor to VCC – 2.0 V.

thermally connected to the die for improved heat transfer out
of package. The pad is not electrically connected to the die,
but is recommended to be electrically connected to GND on
the PC board.

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NB4N441

Table 2. STANDARD PROTOCOL / OUTPUT FREQUENCY SELECT TABLE WITH 27 MHz CRYSTAL REFERENCE

Input Prescaler

# Protocol CLKOUT (MHz)

0 OC−3 /STM−1 155.52 11001 1001000000 010

0 OC−12 / STM−4 155.52 11001 1001000000 010

0 OC−48 / STM−16 155.52 11001 1001000000 010

1 ETR 32 11011 1000000000 100

2 OC−1 51.84 11001 1100000000 100

3 Fast Ethernet 50 11011 1100100000 100

3 ESCON 50 11011 1100100000 100

4 FDDI 125 11011 0111110100 010

4 Infiniband 125 11011 0111110100 010

4 Gigabit Ethernet 125 11011 0111110100 010

4 PCIe 125 11011 0111110100 010

5 1/8 Fibre Channel 13.28125 11011 0110101001 101

6 1/4 Fibre Channel 26.5625 11011 1101010010 101

7 1/2 Fibre Channel 53.125 11011 1101010010 100

8 Fibre Channel 106.25 11011 1101010010 011

9 General 150 11011 1001011000 010

10 D1 Video 69 11011 1000101000 011

11 SONET Reference 19.44 11001 1001000000 101

12 2x Fibre Channel 212.5 11011 1101010010 010

13 4x Fibre Channel 425 11011 1101010010 001

14 XAUI 156.25 11011 1001110001 010

15 Serial ATA 100 11011 1100100000 011

16 HDTV 74.25 11011 1001010010 011

17 HDTV 148.50 11011 1001010010 010

Divider P[4:0]

PLL FB Divider

M[9:0]

Output Frequency Divider

OUTDIV N[2:0]

Table 3. N−DIVIDER TABLE

N2 N1 N0 N Divider

0 0 0 na

0 0 1 B2

0 1 0 B4

0 1 1 B8

1 0 0 B16

1 0 1 B32

1 1 0 na

1 1 1 na

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