© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 1
1 Publication Order Number:
EVBUM2071/D
NB4N11MDTEVB
Evaluation Board User's
Manual for NB4N11M
Description
ON Semiconductor has developed an evaluation board for
the NB4N11M device as a convenience for the customers
interested in performing their own device engineering
assessment. This board provides a high bandwidth 50 W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways.
This NB4N11M evaluation board manual contains:
• Appropriate Lab Setup
• Assembly Instructions
• Bill of Materials
This manual should be used in conjunction with the
NB4N11M device data sheet, which contains full technical
details on the device specifications and operation.
Board Lay−Up
The NB4N11M evaluation board is implemented in four
layers with split (dual) power supplies (Figure 7, Evaluation
Board Lay−up). For standard lab setup, a split (dual) power
supply is essential to enable the 50 W internal impedance in
the oscilloscope as a devices termination. The first layer or
primary trace layer is 0.005″ thick Rogers RO4003 material,
which is designed to have equal electrical length on all signal
traces from the device under the test (DUT) to the sense
output. The second layer is the 1.0 oz copper ground plane.
The FR4 dielectric material is placed between second and
third layer and between third and fourth layer. The third
layer is also 1.0 oz copper ground plane. The fourth layer is
the secondary trace layer.
Top View Bottom View
Figure 1. Top and Bottom View of the NB4N11M Evaluation Board
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EVAL BOARD USER’S MANUAL
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Figure 2. Top & Bottom Layers (Top View)
V
EE
SMA_GND
V
CC
TOP LAYER BOTTOM LAYER
V
EE
SMA_GND
V
CC
Figure 3. Evaluation Board Lay−up
Connecting Power and Ground Planes
The side launch 9 pin power supply connector is wired as
shown in Figure 4. Test points can be soldered on the top of
the PCB to accommodated easier connections. Exact values
that need to be applied can be found in Table 1.
Table 1. Power Supply Levels
Power Supply Span V
TT
(Termination)
V
CC
(Pin 8)
VEE / GND
(Pin 5)
SMA_GND
(PCB SMA Ground)
3.3 V 1.8 V 1.5 V −1.8 V 0 V
3.3 V 2.5 V 0.8 V −2.5 V 0 V
3.3 V 3.3 V 0 V −3.3 V 0 V
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V
CC
SMA_GND
V
EE
Figure 4. Power Supply Connector − 9 Pin Side
View (Left) and PCB Top View (Right)
NC
NC
V
CC
V
EE
V
CC
V
EE
SMA_GND
C3 = 10 mF; C4 = 10 mF
Stimulus (Generator) Termination
All ECL outputs need to be terminated to V
TT
(VTT =
V
CC
– 2.0 V = GND) via a 50 W resistor. The current board
design utilizes the space for placement of the external
termination resistors. (More information on termination is
provided in AN8020). The 0402 chip resistor pads are
provided on the bottom side of the evaluation board. Solder
the chip resistors to the bottom side of the board between the
appropriate input of the device pin pads and the ground pads
as shown in Figure 5 (for split power supply setup, PCB is
assembled in this configuration).
Figure 5. Expanded Bottom View
C1 = 0.01 mF
C2 = 0.01 mF
R2 = 50 W
R1 = 50 W
Likewise for CML outputs, CML stimulus signal need to
be terminated to V
CC
via a 50 W resistor. To accomplish this
configuration the external termination resistor has to be
moved from SMA_GND ring to V
CC
ring on the bottom of
the board.
For the LVDS configuration Input pin pads of the D0 or
D1 input has to be shorted using 100 W resistor across
differential lines.
DUT Termination
For standard lab setup and test, a split (dual) power supply
is required enabling the 50 W internal impedance in the
oscilloscope to be used as a termination of the signals (in
split power supply setup SMA_GND as a system ground,
V
CC
, and VEE are varied; see Table 1, Power Supply Levels).
Board Components Configuration
The NB4N11MDTEVB evaluation board requires six
side SMA connectors. Placement locations are described in
the Table 2 below.
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Table 2. SMA Connector and Jumper Placement
Device J1/Q0 J2/Q0 J3/Q1 J4/Q1 J5 J6/D J7/D J8
Pin # 1 2 3 4 5 6 7 8
Connector Yes Ye s Ye s Ye s No Ye s Yes No
Resistor
(bottom)
0402*
50 W
0402*
50 W
0402*
50 W
0402*
50 W
0402
0.01 mF
0402
50 W
0402
50 W
0402
0.01 mF
Wire No No No No to V
EE
No No to V
CC
*Optional components for 25 W load. Not populated in production
.
Figure 6. Lab Setup
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
IN2
IN3
OUT1
OUT2
OUT3
OUT4
PIN 1
D
D
Q0
Q0
Q1
Q1
SIGNAL
GENERATOR
OSCILLOSCOPE
(50 W Scope Head)
1. Connect appropriate power supplies to VCC, VEE,
and SMA_GND (See Table 1)
2. Connect a signal generator to the input SMA
connectors via matched cables. Setup input signal
according to the device data sheet
3. Connect a test measurement device on the device
output SMA connectors via matched cables.
NOTE: The test measurement device must contain 50 W
termination.
Figure 7. PCB Schematic for 50 W Load
(PCB is assembled in this configuration)
SMA
SMA
SMA
SMA
SMA
SMA
C1
0.01 mF
C3
10 mF
C2
0.01 mF
C4
10 mF
V
CC
R1
50 W
R2
50 W
NB4N11M
1
2
3
4
7
6
5
8
V
EE
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
SIGNAL
GENERATOR
OSCILLOSCOPE
(50 W Scope Head)
D
D
Q0
Q0
Q1
Q1
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Figure 8. PCB Schematic for 25 W Load
(50 W output resistors (Q0, Q0
, Q1, Q1) not assembled )
SMA
SMA
SMA
SMA
SMA
SMA
0.01 mF10 mF
0.01 mF
10 mF
V
CC
50 W
50 W
NB4N11M
1
2
3
4
7
6
5
8
V
EE
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
Z = 50 W
SIGNAL
GENERATOR
OSCILLOSCOPE
(50 W Scope Head)
D
D
Q0
Q0
Q1
Q1
50 W*
*50 W resistors must be added for 25 W load configuration
50 W*
50 W*
50 W*
Table 3. Bill of Materials
Components Manufacturer Description Part Number Qty. Web Site
SMA
Connector
Johnson* SMA Connector − Side
Launch
142−0701−851 6 http://www.johnsoncomponents.com
9 Pin D−Sub
Receptacle
Amphenol Connector, Female,
9−Pin, Right Angle
788796−1 1 http://www.amphenol.com
Surface Mount
Test Points{
Keystone*
SMT Miniature Test
Point
5015
3 http://www.keyelco.com
SMT Compact Test
Point
5016
Chip
Capacitor
AVC
Corporation*
0402 0.01 mF " 10%
04025C103KAT2A 2 http://www.avxcorp.com
10 mF " 10%
T491C106K016AS 2
Chip Resistor Panasonic*
0402 50 W " 1%
Precision Thick Film
Chip Resistor
ERJ−2RKF49R9X 2 http://www.panasonic.com
Evaluation
Board
ON
Semiconductor
Micro−10 Evaluation
Board
N/A 1 http://www.onsemi.com
Device
Samples
ON
Semiconductor
Micro−10 Package
Device
NB4N11MM 1 http://www.onsemi.com
*Components are available through most distributors, i.e. www.newark.com, www.Digikey.com
†Surface Mount Test Points can be used for power supply connection in place of power supply cable connector. See Figure 4 for test point
placement.
NB4N11MDTEVB
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6
PACKAGE DIMENSIONS
Micro−10
CASE 846B−03
ISSUE D
S
B
M
0.08 (0.003) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C 0.95 1.10 0.037 0.043
D 0.20 0.30 0.008 0.012
G 0.50 BSC 0.020 BSC
H 0.05 0.15 0.002 0.006
J 0.10 0.21 0.004 0.008
K 4.75 5.05 0.187 0.199
L 0.40 0.70 0.016 0.028
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−B−
−A−
D
K
G
PIN 1 ID
8 PL
0.038 (0.0015)
−T−
SEATING
PLANE
C
H
J
L
ǒ
mm
inches
Ǔ
SCALE 8:1
10X 10X
8X
1.04
0.041
0.32
0.0126
5.28
0.208
4.24
0.167
3.20
0.126
0.50
0.0196
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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