The NB3N1200KMNGEVB and the NB3W1200LMNG
EVB evaluation boards were developed with a common
PCB layout design to accommodate the NB3N1200K
(standard HCSL outputs) and the NB3W1200L (HCSL
Push-Pull outputs) devices. Each board comes fully
assembled and tested and is ready to evaluate in the lab. This
evaluation board was designed to provide a flexible and
convenient platform to quickly evaluate, characterize and
verify the operation of the NB3N1200K or NB3W1200L
devices. To minimize the board size, six differential outputs
are accessed with SMA connectors. The other six
differential outputs are loaded, terminated and can be
monitored with ahigh impedance probe as explained later in
the manual.
The NB3N1200K Evaluation Board schematic is the
same as the NB3W1200L schematic except the “1200L” has
some components depopulated (DNI) per the “1200L”
BOM.
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EVAL BOARD USER’S MANUAL
• The NB3W1200LMNGEVB does not have RP resistors
installed on its differential Push-Pull outputs.
• The NB3W1200LMNGEVB does not have
FB_OUT/FB_OUT# resistors installed.
• The NB3W1200LMNGEVB does not have R
resistor R107 installed.
This manual should be used in conjunction with the device
datasheet which contains full technical details on the device
specifications and operation.
This evaluation board manual contains:
REF
• Information on the NB3N1200K/NB3W1200L
Evaluation Board
• Assembly Instructions
• Test and Measurement Setup Procedures
• Board Schematic and Bill of Materials
Top ViewBottom View
Figure 1. NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board
1. The NB3N1200K and NB3W1200L have positive
power supply pins VDD and VDDIO. Connect
power supply cables to VDD, VDDIO and GND
banana jacks; (do not turn power on, yet)
2. Connect a signal generator to the SMA connectors
for the CLK_IN & CLK_IN# inputs.
3. 50-ohm termination resistors are installed for
a signal generator on the board. Set appropriate
input signal levels; (HCSL input, VIL = 0 V,
VIH = 700 mV, Frequency 100 or 133.33 MHz)
4. Ensure the PWRGD/PWRDN# pin is in the Low
state before power up (PWRDN#). There is
a jumper on pin 6 to easily select between High
and Low. See Figure 8.
5. The 100M_133M# and HBW_BYPASS_LBW
pins need to be hardware selected with jumpers.
See Figures 4 and 7.
6. To monitor the DIF_n/DIF_n# outputs, connect the
DIF_n/DIF_n# outputs to the appropriate
oscilloscope.
Table 1. POWER SUPPLY CONNECTIONS
Device Pin
Power Supply Connector
VDD3.3 V
VDDIO1.05 V to 3.3 V
GND0V
Single Power Supply
+3.3 V0 V
VDD, VDDIOGND
+3.3 V
Figure 2. Power Supply Connections
+3.3 V0 V
VDDGN
Power Supply
Dual Power Supplies
1.05 V to 3.3 V
VDDIO
1.05 V to 3.3 V
+3.3 V
OscilloscopeSignal Generator
OUT
OUTb
Figure 3. Typical Lab Test Set-Up
Power -Up Sequence
1. Turn on power supply, 3.3 V (VDD & VDDIO).
2. Move PWRGD/PWRDN# jumper from Low to
logic High, PWRGD position.
3. Turn on the Differential Clock Signal for the
CLK_IN inputs. The differential Clock signal for
the CLK_IN inputs can be ON or active before or
after PWRGD is set HIGH.
4. Monitor DIF_n/DIF_n# outputs on oscilloscope.
IN
INb
3.3 V
3.3 V
0 V
Optional
Graphical User Interface
(see page 7)
There is a stand-alone Graphical User Interface software
package and user’s manual that will interface with the DUT
via the USB connector.
1. Connect the USB port on the evaluation board to
a USB port on the PC via cable.
2. See the stand-alone GUI instructions document.
3. Allow Windows to install the necessary drivers for
the eval board USB interface hardware.
4. Start the GUI program.
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2
NB3N1200KMNGEVB, NB3W1200LMNGEVB
Power Supplies
Each VDD, VDDIO and GND power supply has
a separate side-launch banana jack located on bottom side.
This board is capable of measuring device IDD & IDDIO
separately.
Board Layer #2 = SMA Ground = Device GND = 0 V.
GND Banana Jack = negative power supply for
DUTGND and SMAGND.
Exposed Pad (EP): The exposed pad footprint on the
board is soldered to the exposed pad of the QFN-64
package, and is electrically connected to GND power
supply.
Board Layer #3 = VDD and VDDIO Power Supplies
VDD = positive power supply for core and inputs;
VDD/VDDA/VDDR (pins #1, 8, 24, 40, 57)
VDDIO = positive power supply for outputs; VDDIO
(pins #25, 32, 49, 56)
VDD & VDDIO have the power supply filtering per
datasheet by the banana jacks.
All VDD/VDDA/VDDR/VDDIO device pins have
a 0.1 mF bypass capacitor installed on top side next to
package pins.
Control Pins
Each control pin can be managed manually with a H/L
jumper header; H = VDD, L = GND.
Tri-Level Input Pins - HBW_BYPASS_LBW#, SA0 and SA1
The three tri-level input pins, HBW_BYPASS_LBW#,
SA0 and SA1, have selectable (with jumper) 4.7 k-ohm
pull-up to VDD and 4.7 k-ohm pull-down to GND resistors;
No jumper defaults to open/float.
• For a HIGH Level – Put Jumper to High
• For a LOW Level − Put Jumper to Low
• For a MID Level − Put Jumper to both High and Low;
this will Enable both Pull-up and Pull-down Resistors
HBW_BYPASS_LBW#
At J65 and J66 headers, there is a 4.7 kW pull-up to VDD
and a 4.7 kW pull-down resistor to GND for manual control.
See Figure 4.
SA0 & SA1
At J67 and J69 headers, there are 4.7 kW pull-ups to VDD
and at J68 and J70, there are 4.7 kW pull-down resistors to
GND for manual control. See Figure 5.
Six of the twelve differential outputs that have metal
traces going to SMA connectors have OE_n# pins on the left
side of the board that can be controlled manually using the
convenient High/Low OE_n# jumpers. See Figure 6.
OE#
USB GUI
J47
HI − Jumper to VDD
USB − Jumper to Mid
LO − Jumper to GND
Figure 6. OE_n# Pins Schematic/PCB Configuration
100M_133M# - Frequency Selection (J55)
The 100M_133M# frequency selection pin can be
controlled manually with the High/Low header jumper J55,
H = 100 MHz, L = 133 MHz.
All twelve of the OE_n#s can be controlled individually/
automatically by using the software GUI. GUI control is
accomplished via the USB when the OE_n# jumper is
installed on the middle header position. See Figure 6.
The differential Clock input traces, CLK_IN/CLK_IN#,
are equal length routed straight from the SMA connectors on
the left side directly to the DUT; there are no vias on metal
traces.
CLK_IN & CLK_IN# have resistor pads (R51 & R52) to
GND to terminate a signal generator, if used. 50-ohm
resistors are installed. Remove these resistors if CLK_IN
& CLK_IN# are driven by another IC device.
Six of the twelve differential outputs are designed to have
equal length metal traces from the device pins to the SMA
connectors.
The other six differential outputs have shortened metal
traces, do not have SMA connectors and can be observed
with a high-impedance probe on the metal pads provided.
Each DIF_n/DIF_n# output has a provision for C
2 pF capacitors are installed on all outputs.
Rs & Rp pads are located close to the DUT . Rs = 33-W is
installed for both the NB3N1200K and NB3W1200L.
NB3N1200K (HCSL Outputs)
DIF_n and DIF_n# - Differential Outputs
NB3N1200KMNGEVB and NB3W1200LMNGEVB
were designed with a flexible PCB layout configuration to
measure the differential HCSL (1200K) or Push-Pull
(1200L) outputs with a 50-ohm scope head or
RP is not installed on the six output pair with long metal
traces to SMA connectors; Use 50-W to GND of the
oscilloscope head for RP.
Rp is installed (50-W to GND) on the short metal traces
without SMA connectors and will use Hi-Z probes.
high-impedance FET probe. (See Output Layout in
Figures 8 and 9)
NB3W1200L (Push-Pull Outputs)
Rp is not installed
Table 2. NB3N1200KMNGEVB AND NB3W1200LMNGEVB OUTPUT LOAD AND TERMINATION
VS. OSCILLOSCOPE MEASUREMENT
DeviceOutput TracesRsRpCLoadScope
1200KLong
1200KShort
1200LLong or Short
33-W
33-W50-W
33-W
Open (DNI)2pF
2pFHi-Z
Open (DNI)2pFHi-Z
50-W
Load
;
D IF_4
34
DIF_4
DIF_N4
DIF_5
35
D IF_5
38
DIF_N5
39
DIF_4#
DIF_5#
From: DUT Output
From: DUT Output
R33
12
33
R37
12
33
R41
12
33
R45
12
33
12
12
12
12
DIF_5#
DIF_5
DIF_4#
DIF_4
R35
49.9
R39
49.9
R43
49.9
R47
49.9
12
C9
2.0pF
12
C10 2.0pF
120
C11 2.0pF
12
C12 2.0pF
Rs
Rs
OUT4
OUT_N4
Rp
Rp
TP19
TP20
GND
DIF_4
DIF_4#
OUT5
R125
12
R126
12
GND
Long Output Traces:
0
0
PR6
OUT_N5
Use 50-W Scope via SMA Connector
CL
CL is at SMA
Connector
R42
12
R46
12
0
DIF_5#
DIF_5
DIF_4#
Short Output Traces:
Use High-Z Probe
DIF_4
Figure 9. Differential Outputs Schematic/PCB Configuration: Long vs. Short Metal Traces
J11
J12
DIF_5
DIF_5#
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5
NB3N1200KMNGEVB, NB3W1200LMNGEVB
HCSL Output Measurement
HCSL outputs are typically terminated with 50-W to
ground. Measuring HCSL outputs can be easily
accomplished by:
NB3N1200K (HCSL Outputs) − 50-W Oscilloscope Head
With R
removed from board, connect the HCSL outputs
P
through the SMA connectors to the 50-W internal impedance
of the oscilloscope sampling head.
NB3N1200K (HCSL Outputs) − Use Hi-Z Probe
With R
installed, use a high-impedance probe on the
P
output’s metal trace. Holes for headers to connect to Hi-Z
probes are available, but the header pins are not installed.
• Single-ended Hi-Z probes or,
• Differential Hi-Z probe; (see layout below)
Optional component to Ground, if
needed, when shorted to output trace.
Ground
NB3W1200L (Push-Pull Outputs) − Use Hi-Z Probe
Rp is not installed
• A 0-W series resistor is installed between the end of the
transmission line and the SMA connector. This resistor
can be removed, if needed, to eliminate any SMA
impedance/stub when using Hi-Z probes.
• As a feature, an optional component can be installed on
each output, ie. additional capacitance loading etc.
The following figures describe the boards’ output
features:
C
(2 pF), installed
Load
Series R = 0-W installed
Hi-Z probe
From: DUT Output
Figure 10. Differential Outputs Schematic/PCB Configuration: Use Hi-Z Probe Scope for NB3W1200L
Misc. Pins
FB_OUT & FB_OUT# − External Termination
of Feedback Pins
FB_OUT & FB_OUT# have convenient “test point
anvils” to monitor these pins with Hi-Z probe.
NB3N1200K (HCSL):
Since the FB_OUT & FB_OUT# pins do not drive
transmission lines (no SMAs), the board layout has these
pins loaded/terminated at the DUT per datasheet; 83-W to
GND is installed for the 100-W board.
NB3W1200L (Push-Pull):
FB_OUT & FB_OUT# resistors are not installed.
Short with 0-W resistor for use
with Hi-Z probe; 0-W installed.
IREF Pin
NB3N1200K (HCSL):
The R
resistor (R107) to GND for the HCSL output
REF
part device.
= 475-W is installed for the 100-W board.
R
REF
NB3W1200L (Push-Pull)
R
is not installed for the NB3W1200L device.
REF
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6
NB3N1200KMNGEVB, NB3W1200LMNGEVB
Graphical User Interface (GUI)
USB & I2C/SMBus Interface
The NB3N1200K EVB has an on-board I
interface circuitry located in the upper left section of the
board.
This circuitry will interface with the software program
and the device via the SDA and SCL input pins, and can
control all twelve of the OE_n# pins, PLL Mode and
Frequency Select directly from the GUI.
SCL & SDA
The SMBus Clock (SCL) and Data (SDA) pins are
exercised through the on-board I
Single Board Design/Layout for NB3N1200K or
NB3W1200L:
2
C interface.
2
C/SMBus
BOARD FEATURES
• The single board design and layout accommodates the
electrical characterization of either the NB3N1200K
(standard HCSL outputs) or the NB3W1200L (HCSL
Push-Pull outputs).
• Incorporates on-board I
powered from a USB connection, minimizing cabling.
2
C/SMBus interface circuitry
• Convenient and compact board layout.
• 3.3 V power supply device operation.
• Differential inputs/outputs signals are accessed via
SMA connectors or high impedance probes.
2
In order to enable the I
jumpers J63 & J64 must be shorted.
2
The I
C/SMBus interface circuitry is powered separately
from the USB type-B connection and is isolated from device
VDD and VDDIO.
The SDA and SCL pins can also be externally accessed by
an off-board programmer , allowing other SMBus emulators
to be used to program the DUT. If used, remove both jumpers
J63 & J64. “Test-point anvils” TP5 & TP6 are available for
external control of the device with the use with mini-grabber
cables.
environment (100-W line-to-line differential) and is
implemented in four layers.
C control of the DUT, header
• All layers are constructed with FR4 dielectric material.
• The first layer is the primary signal layer, including all
of the differential inputs and outputs.
• The second layer is the ground plane. It is dedicated for
the DUT ground/SMA ground plane.
• The third layer is dedicated as the power plane.
rd
A portion of this 3
VDD and VDDIO power planes.
layer is designated for the device
• The fourth layer contains control lines, power supply
banana jacks and device power pin bypass capacitors.
Other Board Features
There are no vias on the high-speed differential I/O metal
traces so as to eliminate via impedance and stub affects.
Board stand-offs are installed.
Board Layout
The NB3N1200K QFN-64 Evaluation Board provides
a high bandwidth, 50-W controlled trace impedance
Figure 11. NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board Layer Stack-Up
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