ON Semiconductor NB3N1200KMNGEVB, NB3W1200LMNGEVB, NB3N1200K, NB3W1200L User Manual

NB3N1200KMNGEVB,
NB3W1200LMNGEVB

NB3N1200K/NB3W1200L
Evaluation Board
User'sManual

Introduction

The NB3N1200KMNGEVB and the NB3W1200LMNG
EVB evaluation boards were developed with a common
PCB layout design to accommodate the NB3N1200K
(standard HCSL outputs) and the NB3W1200L (HCSL
Push-Pull outputs) devices. Each board comes fully
assembled and tested and is ready to evaluate in the lab. This
evaluation board was designed to provide a flexible and
convenient platform to quickly evaluate, characterize and
verify the operation of the NB3N1200K or NB3W1200L
devices. To minimize the board size, six differential outputs
are accessed with SMA connectors. The other six
differential outputs are loaded, terminated and can be
monitored with ahigh impedance probe as explained later in
the manual.

The NB3N1200K Evaluation Board schematic is the
same as the NB3W1200L schematic except the “1200L” has
some components depopulated (DNI) per the “1200L”
BOM.

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EVAL BOARD USER’S MANUAL

• The NB3W1200LMNGEVB does not have RP resistors

installed on its differential Push-Pull outputs.

• The NB3W1200LMNGEVB does not have

FB_OUT/FB_OUT# resistors installed.

• The NB3W1200LMNGEVB does not have R

resistor R107 installed.

This manual should be used in conjunction with the device
datasheet which contains full technical details on the device
specifications and operation.

This evaluation board manual contains:

REF

• Information on the NB3N1200K/NB3W1200L

Evaluation Board

• Assembly Instructions

• Test and Measurement Setup Procedures

• Board Schematic and Bill of Materials

Top View Bottom View

Figure 1. NB3N1200KMNGEVB and NB3W1200LMNGEVB Evaluation Board

© Semiconductor Components Industries, LLC, 2013

December, 2013 − Rev. 0

1 Publication Order Number:

EVBUM2216/D

NB3N1200KMNGEVB, NB3W1200LMNGEVB

D

QUICK START LAB SET-UP USER’S GUIDE

Pre-Power-Up

1. The NB3N1200K and NB3W1200L have positive
power supply pins VDD and VDDIO. Connect
power supply cables to VDD, VDDIO and GND
banana jacks; (do not turn power on, yet)

2. Connect a signal generator to the SMA connectors
for the CLK_IN & CLK_IN# inputs.

3. 50-ohm termination resistors are installed for
a signal generator on the board. Set appropriate
input signal levels; (HCSL input, VIL = 0 V,
VIH = 700 mV, Frequency 100 or 133.33 MHz)

4. Ensure the PWRGD/PWRDN# pin is in the Low
state before power up (PWRDN#). There is
a jumper on pin 6 to easily select between High
and Low. See Figure 8.

5. The 100M_133M# and HBW_BYPASS_LBW
pins need to be hardware selected with jumpers.
See Figures 4 and 7.

6. To monitor the DIF_n/DIF_n# outputs, connect the
DIF_n/DIF_n# outputs to the appropriate
oscilloscope.

Table 1. POWER SUPPLY CONNECTIONS

Device Pin

Power Supply Connector

VDD 3.3 V

VDDIO 1.05 V to 3.3 V

GND 0V

Single Power Supply

+3.3 V 0 V

VDD, VDDIO GND

+3.3 V

Figure 2. Power Supply Connections

+3.3 V 0 V

VDD GN

Power Supply

Dual Power Supplies

1.05 V to 3.3 V

VDDIO

1.05 V to 3.3 V

+3.3 V

OscilloscopeSignal Generator

OUT

OUTb

Figure 3. Typical Lab Test Set-Up

Power -Up Sequence

1. Turn on power supply, 3.3 V (VDD & VDDIO).

2. Move PWRGD/PWRDN# jumper from Low to
logic High, PWRGD position.

3. Turn on the Differential Clock Signal for the
CLK_IN inputs. The differential Clock signal for
the CLK_IN inputs can be ON or active before or
after PWRGD is set HIGH.

4. Monitor DIF_n/DIF_n# outputs on oscilloscope.

IN
INb

3.3 V

3.3 V

0 V

Optional
Graphical User Interface

(see page 7)

There is a stand-alone Graphical User Interface software
package and user’s manual that will interface with the DUT
via the USB connector.

1. Connect the USB port on the evaluation board to
a USB port on the PC via cable.

2. See the stand-alone GUI instructions document.

3. Allow Windows to install the necessary drivers for
the eval board USB interface hardware.

4. Start the GUI program.

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NB3N1200KMNGEVB, NB3W1200LMNGEVB

Power Supplies

Each VDD, VDDIO and GND power supply has

a separate side-launch banana jack located on bottom side.

This board is capable of measuring device IDD & IDDIO

separately.

Board Layer #2 = SMA Ground = Device GND = 0 V.

GND Banana Jack = negative power supply for
DUTGND and SMAGND.
Exposed Pad (EP): The exposed pad footprint on the
board is soldered to the exposed pad of the QFN-64
package, and is electrically connected to GND power
supply.

Board Layer #3 = VDD and VDDIO Power Supplies

VDD = positive power supply for core and inputs;
VDD/VDDA/VDDR (pins #1, 8, 24, 40, 57)

VDDIO = positive power supply for outputs; VDDIO
(pins #25, 32, 49, 56)

VDD & VDDIO have the power supply filtering per

datasheet by the banana jacks.

All VDD/VDDA/VDDR/VDDIO device pins have
a 0.1 mF bypass capacitor installed on top side next to
package pins.

Control Pins

Each control pin can be managed manually with a H/L

jumper header; H = VDD, L = GND.

Tri-Level Input Pins - HBW_BYPASS_LBW#, SA0 and SA1

The three tri-level input pins, HBW_BYPASS_LBW#,
SA0 and SA1, have selectable (with jumper) 4.7 k-ohm
pull-up to VDD and 4.7 k-ohm pull-down to GND resistors;
No jumper defaults to open/float.

• For a HIGH Level – Put Jumper to High

• For a LOW Level − Put Jumper to Low

• For a MID Level − Put Jumper to both High and Low;

this will Enable both Pull-up and Pull-down Resistors

HBW_BYPASS_LBW#

At J65 and J66 headers, there is a 4.7 kW pull-up to VDD
and a 4.7 kW pull-down resistor to GND for manual control.
See Figure 4.

SA0 & SA1

At J67 and J69 headers, there are 4.7 kW pull-ups to VDD
and at J68 and J70, there are 4.7 kW pull-down resistors to
GND for manual control. See Figure 5.

SA0 SA1

VDD

R57

12

4.7K

J65

HBW HI

12

J66

12

HBW LO

HBW

R58

12

4.7K

Figure 4. HBW_BYPASS_LBW# Schematic/PCB Configuration

GND

VDD

GND

VDD

VDD

VDD

R79

12

4.7K

R85

12

4.7K

J67

12

SA0 HI

J69

12

SA1 HI

J68

12

SA0 LO

J70

12

SA1 LO

Figure 5. SA0 & SA1 Schematic/PCB Configuration

5

HBW_BYP_LBW

SA0

R82

12

4.7K

SA1

R88

12

4.7K

11

14

SA0

SA1

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Control Pins (Continued)

NB3N1200KMNGEVB, NB3W1200LMNGEVB

OE_n# Pins (Output Enable/Disable Function)

Six of the twelve differential outputs that have metal
traces going to SMA connectors have OE_n# pins on the left
side of the board that can be controlled manually using the
convenient High/Low OE_n# jumpers. See Figure 6.

OE#

USB GUI

J47

HI − Jumper to VDD

USB − Jumper to Mid

LO − Jumper to GND

Figure 6. OE_n# Pins Schematic/PCB Configuration

100M_133M# - Frequency Selection (J55)

The 100M_133M# frequency selection pin can be
controlled manually with the High/Low header jumper J55,
H = 100 MHz, L = 133 MHz.

All twelve of the OE_n#s can be controlled individually/
automatically by using the software GUI. GUI control is
accomplished via the USB when the OE_n# jumper is
installed on the middle header position. See Figure 6.

37

12
34
56

VDD

OE#

1

J55

2
3

Figure 7. 100M_133M# Pin Schematic/PCB Configuration

PWRGD/PWRDN# (J56)

The PWRGD/PWRDN# pin can be controlled manually
with the High/Low header jumper J56; H = PWRGD,
L = PWRDN#.

1

J56

Figure 8. PWRGD/PWRDN# Pin Schematic/PCB Configuration

2
3

VDD

VDD

4

100M_133M_N

6

PWRGD

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