3.3 V 200 MHz 1:2
LVCMOS/LVTTL Low Skew
Fanout Buffer
Description
The NB3M8302C is 1:2 fanout buffer with LVCMOS/LVTTL input
and output. The device supports the core supply voltage of 3.3 V (V
pin) and output supply voltage of 2.5 V or 3.3 V (V
V
pin powers the two single ended LVCMOS/LVTTL outputs.
DDO
DDO
pin). The
DD
The NB3M8302C is Form, Fit and Function (pin to pin) compatible
to ICS8302 and ICS8302I. The NB3M8302C is qualified for industrial
operating temperature range.
Features
• Input Clock Frequency up to 200 MHz
• Low Output to Output Skew: 25 ps typical
• Low Part to Part Skew: 250 ps typical
• Low Additive RMS Phase Jitter
• Input Clock Accepts LVCMOS/ LVTTL Levels
• Operating Voltage:
♦ Core Supply: V
♦ Output Supply: V
= 3.3 V ±5%
DD
= 3.3 V ±5% or 2.5 V ±5%
DDO
• Operating Temperature Range:
♦ Industrial: −40°C to +85°C
• These Devices are Pb−Free and are RoHS Compliant
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MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
A= Assembly Location
L= Wafer Lot
Y= Year
W= Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. For additional information, see Application Note AND8003/D.
Power Supply−4.6V
Input Voltage−0.5VDD + 0.5 VV
I
Storage Temperature−65+150
Thermal Resistance (Junction to Ambient)
SOIC−8
0 lfpm
500 lfpm
Thermal Resistance (Junction to Case)
(Note 1)
Wave Solder3 sec265
Indefinite Time Out of Drypack
SOIC−8
(Note 2)Level 1
80
55
12−17
_C
_C/W
_C/W
_C
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2
NB3M8302C
Table 3. DC OPERATING CHARACTERISTICS
= V
(V
DD
Symbol
R
C
R
OUT
C
V
I
I
3. Outputs terminated with 50 W to V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
= 2.5 V±5%; TA = −40°C to +85°C)
DDO
VDD = V
VDD = 3.465 V, V
= 3.465 V22
DDO
= 2.625 V16
DDO
kW
W
pF
mA
mA
Table 4. DC OPERATING CHARACTERISTICS (T
Symbol
VDD = 3.3 V+5%, V
V
DDO
V
OH
V
OL
VDD = V
V
DDO
V
OH
V
OL
Output Supply Voltage2.3752.625V
Output HIGH Voltage
Output LOW Voltage
= 3.3 V+5%
DDO
Output Supply Voltage3.1353.465V
Output HIGH Voltage
Output LOW Voltage
DDO
ParameterConditionMinMaxUnit
= 2.5 V+5%
= −40°C to +85°C)
A
IOH = −16 mA2.1
IOH = −100 mA
50 W to V
IOL = 100 mA
50 W to V
IOH = −16 mA2.9
IOH = −100 mA
50 W to V
IOL = 100 mA
50 W to V
2.2
DDO
/2
1.8
IOL = 16 mA0.15
0.2
DDO
/2
0.5
2.9
DDO
/2
2.6
IOL = 16 mA0.15
0.2
DDO
/2
0.5
V
V
V
V
Table 5. DC OPERATING CHARACTERISTICS (T
V±5%)
Symbol
I
DD
I
DDO
V
IH
V
IL
Quiescent Power Supply CurrentNo Load13mA
Quiescent Power Supply CurrentNo Load4mA
Input HIGH Voltage2VDD + 0.3V
Input LOW Voltage−0.31.3V
ParameterConditionMinMaxUnit
= −40°C to +85°C; VDD = V
A
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3
= 3.3 V±5%, VDD = 3.3 V±5%, V
DDO
DDO
= 2.5
NB3M8302C
Table 6. AC CHARACTERISTICS (Note 4)
Symbol
TA = −405C to +855C; VDD = V
F
t
PLH
t
SKEW
Input Frequency200MHz
IN
Propagation Delay (Note 5)Fin = 200 MHz1.93.1ns
Output to Output Skew(Note 6)2585
Part to Part Skew (Note 6)250800
t
SKEWDC
Output Duty Cycle (see Figure 3)
tr/tfOutput rise and fall times (Note 7)
TA = −405C to +855C; VDD = 3.3 V+5%, V
F
t
PLH
t
SKEW
Input Frequency200MHz
IN
Propagation Delay (Note 5)Fin = 200 MHz2.03.3ns
Output to Output Skew(Note 6)2585
Part to Part Skew (Note 6)250800
t
SKEWDC
Output Duty Cycle (see Figure 3)
tr/tfOutput rise and fall times (Note 7)
4. Clock input with 50% duty cycle. Outputs terminated with 50 W to V
5. Measured from V
6. Similar input conditions and the same supply voltages. Measured at V
/2 of the input to V
DD
7. RS is Series Resistance at the clock outputs.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
ParameterConditionMinTypMaxUnit
= 3.3 V+5%
DDO
ps
Fin v 133 MHz4555
%
133 MHz < Fin < 200 MHz4060
250800ps
= 2.5 V+5%
DDO
20% to 80%, RS = 33 W
ps
Fin v 133 MHz4555
%
133 MHz < Fin < 200 MHz4060
200650ps
/2 of the output.
DDO
20% to 80%, RS = 33 W
/2. See Figures 3 and 4.
DDO
/2. See Figures 3 and 4.
DDO
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4
NB3M8302C
Figure 3. AC Reference Measurement
V
DD
V
DDO
ZO = 50 W
NB3M8302CReceiver /
QxD
Scope
50 W
DUT
GND
Spec Condition:TEST SETUP VDD:TEST SETUP V
VDD = V
V
= 3.3 V ±5%1.65 V ±5%1.65 V ±5%−1.65 V ±5%
DDO
VDD = 3.3 V ±5%;
= 2.5 V ±5%
DDO
2.05 V ±5%1.25 V ±5%−1.25 V ±5%
:TEST SETUP DUT GND:
DDO
Figure 4. Output Driver Typical Device Evaluation and Termination Setup
ORDERING INFORMATION
DevicePackageShipping
NB3M8302CDGSOIC−8
98 Units / Rail
(Pb−Free)
NB3M8302CDR2GSOIC−8
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
†
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
8
1
SCALE 1:1
−Y−
−Z−
−X−
A
58
B
1
4
G
H
D
0.25 (0.010)Z
M
SOLDERING FOOTPRINT*
7.0
0.275
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
0.060
0.10 (0.004)
1.52
4.0
0.155
CASE 751−07
M
M
Y
N
SOIC−8 NB
ISSUE AK
K
X 45
_
M
J
MARKING DIAGRAM*
8
XXXXX
ALYWX
1
XXXXX = Specific Device Code
A= Assembly Location
L= Wafer Lot
Y= Year
W= Work Week
G= Pb−Free Package
8
XXXXX
ALYWX
G
1
IC
IC
(Pb−Free)
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
XXXXXX = Specific Device Code
A= Assembly Location
Y= Year
WW= Work Week
G= Pb−Free Package
8
XXXXXX
AYWW
1
Discrete
(Pb−Free)
G
0.6
0.024
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
SOIC−8 NB
CASE 751−07
ISSUE AK
STYLE 3:
STYLE 7:
STYLE 11:
STYLE 15:
STYLE 19:
STYLE 23:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
DATE 16 FEB 2011
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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