ON Semiconductor N24S128 User Manual

N24S128

128 Kb I2C CMOS Serial
EEPROM with Software
Write Protect and
Programmable Device
Address

Description

The N24S128 is a 128 Kb Serial CMOS EEPROM, internally

organized as 816,384 words of 8 bits each.

They feature a 64-byte page write buffer and support both the
Standard (100 kHz), Fast (400 kHz) and Fast-Plus (1 MHz) I
protocol.

The devices also feature a 128-bit factory-set read-only Unique ID,
a 64-byte Secure Data Page that can be permanently locked against
future changes, and Software Write Protection of the entire array.
A Device Configuration Register enables the user to specify the last
3 bits of the Device Address, allowing up to eight N24S128 devices to
be addressed on the same bus.

Features

• Supports Standard, Fast and Fast-Plus I

2

C Protocol

• 1.7 V to 5.5 V Supply Voltage Range

• 64-byte Page Write Buffer

• Lockable Secure Data Page

• User Programmable Write Protection

• User Programmable Device Address

• Schmitt Triggers and Noise Suppression Filters on I

(SCL and SDA)

2

C Bus Inputs

• Low Power CMOS Technology

• 1,000,000 Program/Erase Cycles

• 100 Year Data Retention

• Industrial Temperature Range: −40°C to +85°C

• Ultra-thin 4-ball WLCSP Package

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant*

V

CC

2

C

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WLCSP−4

C4 SUFFIX

CASE 567VY

PIN CONFIGURATION

12

ABV

SDA V

PIN FUNCTION

Pin Name Function

SDA

SCL

V

CC

V

SS

MARKING DIAGAM

X = Specific Device Code

(See Ordering Information Table)
Y = Production Year (Last Digit)
W = Production Week Code

SCL

CC

SS

(Top View)

Serial Data Input/Output

Serial Clock Input

Power Supply

Ground

X

YW

N24S128

V

SS

Figure 1. Functional Symbol

© Semiconductor Components Industries, LLC, 2017

April, 2019 − Rev. 2

ORDERING INFORMATION

See detailed ordering and shipping information on page 9 of

SDASCL

1 Publication Order Number:

this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

N24S128/D

N24S128

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

Storage Temperature −65 to +150

Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
undershoot to no less than −1.5 V or overshoot to no more than V

+ 1.5 V, for periods of less than 20 ns.

CC

+ 1.0 V. During transitions, the voltage on any pin may

CC

Table 2. RELIABILITY CHARACTERISTICS (Note 2)

Symbol

N

(Note 3) Endurance 1,000,000 Program/Erase Cycles

END

T

(Note 4) Data Retention 100 Years

DR

2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.

3. Page Mode, V

= 55_C

4. T

A

= 5 V, 25_C

CC

Parameter Min Unit

Table 3. DC AND AC OPERATING CONDITIONS

Supply Voltage / Temperature Range Operation

V

= 1.7 V to 5.5 V / T

CC

V

= 1.6 V to 5.5 V / T

CC

V

= 1.6 V to 5.5 V / T

CC

= −40°C to +85°C

A

= −40°C to +85°C

A

= 0°C to +85°C

A

READ / WRITE

READ

WRITE

°C

Table 4. D.C. OPERATING CHARACTERISTICS

Symbol Parameter Test Conditions Min Max Unit

I

CCR

I

CCW

I

V

V

V

V

V

V

SB

I

L

IL1

IL2

IH1

IH2

OL1

OL2

Read Current

Write Current

Standby Current

I/O Pin Leakage

Input Low Voltage

Input Low Voltage V

Input High Voltage

Input High Voltage V

Output Low Voltage

Output Low Voltage

Read, f

All I/O Pins at GND or V

Pin at GND or V

V

CC

CC

V

CC

CC

V

CC

V

CC

= 400 kHz/1 MHz

SCL

1 mA

2 mA

V

V

CC

CC

< 2.5 V

> 2.5 V

−0.5 0.3 V

0.7 V

CC

CC

CC

CC

≥ 2.5 V

< 2.5 V −0.5 0.25 V

≥ 2.5 V

< 2.5 V 0.75 V

≥ 2.5 V, IOL = 3.0 mA

< 2.5 V, IOL = 1.0 mA

1 mA

2

2

V

CC

V

CC

0.4 V

0.2 V

CC

CC

+ 1 V

+ 1 V

mA

V

V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Table 5. PIN IMPEDANCE CHARACTERISTICS

Symbol Parameter Conditions Max Unit

C

(Note 5) SDA I/O Pin Capacitance V

IN

C

(Note 5) Input Capacitance (other pins) V

IN

5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.

= 0 V 8 pF

IN

= 0 V 6 pF

IN

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N24S128

Table 6. A.C. CHARACTERISTICS (Note 6)

Standard

= 1.7 to 5.5

V

CC

= −40 to 855C

T

A

Symbol

F

SCL

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

t

(Note 7) SDA and SCL Rise Time 1,000 20 300 100

R

t

(Note 7) SDA and SCL Fall Time 300 20 300 100

F

t

SU:STO

t

BUF

t

AA

t

DH

T

(Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 50 50

i

t

WR

T

PU

(Notes 7, 8)

Clock Frequency 100 400 1,000

START Condition Hold Time 4 0.6 0.26

Low Period of SCL Clock 4.7 1.3 0.5

High Period of SCL Clock 4 0.6 0.26

START Condition Setup Time 4.7 0.6 0.26

Data In Hold Time 0 0 0

Data In Setup Time 250 100 50

STOP Condition Setup Time 4 0.6 0.25

Bus Free Time Between STOP and START 4.7 1.3 0.5

SCL Low to Data Out Valid 3.5 0.9 0.40

Data Out Hold Time 100 100 50

Write Cycle Time 5 5 5

Power-up to Ready Mode 0.35 0.35 0.35

Parameter

Min Max Min Max Min Max

6. Test conditions according to “A.C. Test Conditions” table.

7. Tested initially and after a design or process change that affects this parameter.

is the delay between the time VCC is stable and the device is ready to accept commands.

8. t

PU

Fast

= 1.7 to 5.5

V

CC

= −40 to 855C

T

A

Fast−Plus

V

CC

= −40 to 855C

T

A

= 1.7 to 5.5

Unit

kHz

ms

ms

ms

ms

ms

ns

ns

ns

ms

ms

ms

ns

ns

ms

ms

Table 7. A.C. TEST CONDITIONS

Parameter Condition

Input Levels 0.2 × V

Input Rise and Fall Times

≤ 50 ns

to 0.8 × V

CC

Input Reference Levels 0.3 × VCC, 0.7 × V

Output Reference Levels 0.5 × V

Output Load

CC

Current Source: I

10

1

120 ns Rise Time

Pull-up Resistance (kW)

0.1
10

Load Capacitance (pF)

Figure 2. Maximum Pull-up Resistance vs. Load Capacitance

CC

CC

= 3 mA (V

OL

CC

300 ns Rise Time

100

≥ 2.5 V); I

= 1 mA (V

OL

< 2.5 V); C

CC

SDA

= 100 pF

L

V

CC

R

P

C

L

V

SS

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N24S128

Power-On Reset (POR)

The N24S128 incorporates Power-On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.

The N24S128 will power up into Standby mode after V

CC

exceeds the POR trigger level and will power down into
Reset mode when V

drops below the POR trigger level.

CC

This bi-directional POR feature protects the device against
‘brown-out’ failure following a temporary loss of power.

Pin Description

• SCL: The Serial Clock input pin accepts the Serial

Clock generated by the Master.

• SDA: The Serial Data I/O pin receives input data and

transmits data stored in EEPROM. In transmit mode,
this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.

Functional Description

The N24S128 supports the Inter-Integrated Circuit (I2C)
Bus data transmission protocol, which defines a device that
sends data to the bus as a transmitter and a device receiving
data as a receiver. Data flow is controlled by a Master device,
which generates the serial clock and all START and STOP
conditions. The N24S128 acts as a Slave device. Master and
Slave alternate as either transmitter or receiver. Up to 8
devices may be connected to the bus as determined by the
Device Address bits A
Configuration Register.

2

C Bus Protocol

I

2

The I

C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
resistors. Master and Slave devices connect to the 2-wire bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.

, A1, and A2 in the Device

0

supply via pull-up

CC

Data transfer may be initiated only when the bus is not

busy (see A.C. Characteristics).

During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 3). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake-up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.

Device Addressing

The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations, and to 1011
for special Read/Write operations (Figure 4). The next 3 bits
must match the A2, A1, A0 bits in the Device Configuration
Register. The last bit, R/W, specifies whether a Read (1) or
Write (0) operation is to be performed.

The factory default for the A2, A1, A0 bits is 0.

Acknowledge

After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9

th

clock cycle (Figure 5). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode if the addressed location is not write
protected. In Read mode the Slave shifts out a data byte, and
then releases the SDA line during the 9

th

clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 6.

SCL

SDA

START

CONDITION

STOP

CONDITION

Figure 3. START/STOP Conditions

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