ON Semiconductor MT9V023 Users manual

MT9V023

1/3-Inch Wide‐VGA CMOS Digital Image Sensor

General Description

The ON Semiconductor MT9V023 is a 1/3-inch wide-VGA format CMOS active-pixel digital image sensor with global shutter and high dynamic range (HDR) operation. The sensor has specifically been designed to support the demanding interior and exterior automotive imaging needs, which makes this part ideal for a wide variety of imaging applications in real-world environments.

This wide-VGA CMOS image sensor features ON Semiconductor’s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.

The active imaging pixel array is 752 H x 480 V. It incorporates sophisticated camera functions on-chip-such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions-as well as windowing, column and row mirroring. It is programmable through a simple two-wire serial interface.

The MT9V023 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other parameters. The default mode outputs a wide-VGA-size image at 60 frames per second (fps).

An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolution companded for 10 bits for small signals can be alternatively enabled, allowing more accurate digitization for darker areas in the image.

In addition to a traditional, parallel logic output the MT9V023 also features a serial low-voltage differential signaling (LVDS) output. The sensor can be operated in a stereo-camera, and the sensor, designated as a stereo-master, is able to merge the data from itself and the stereo-slave sensor into one serial LVDS stream.

The sensor is designed to operate in a wide temperature range (–40°C to +105°C).

Features

• Array Format: Wide-VGA, Active 752 H x 480 V (360,960 pixels)

• Global Shutter Photodiode Pixels; Simultaneous Integration and

Readout

• Monochrome or Color: NIR Enhanced Performance for Use with

Non-visible NIR Illumination

• Readout Modes: Progressive or Interlaced

• Shutter Efficiency: >99%

• Simple Two-wire Serial Interface

• Real-time Exposure Context Switching - Dual Registerset

• Register Lock Capability

• Window Size: User Programmable to any Smaller Format (QVGA,

CIF, QCIF). Data Rate can be Maintained Independent of Window Size

• Binning: 2 x 2 and 4 x 4 of the Full Resolution

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IBGA52 9x9

CASE 503AA

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of this data sheet.

• ADC: On-chip, 10-bit Column-parallel

(Option to Operate in 12-bit to 10-bit Companding Mode)

• Automatic Controls: Auto Exposure Control

(AEC) and Auto Gain Control (AGC); Variable Regional and Variable Weight AEC/AGC

• Support for Four Unique Serial Control

• Data Output Formats:

• Single Sensor Mode:

10-bit Parallel/Stand-alone 8-bit or 10-bit Serial LVDS

• Stereo Sensor Mode:

Interspersed 8-bit Serial LVDS

• High Dynamic Range (HDR) Mode

Applications

• Automotive

• Unattended Surveillance

• Stereo Vision

• Smart Vision

• Automation

• Video as Input

• Machine Vision

January, 2017 − Rev. 6

1 Publication Order Number:

MT9V023/D

MT9V023

Table 1. KEY PERFORMANCE PARAMETERS

Parameter Value

Optical Format 1/3-inch

Active Imager Size 4.51 mm (H) x 2.88 mm (V)

Active Pixels 752 H x 480 V

Pixel Size 6.0 x 6.0 μm

Color Filter Array Monochrome or color RGB Bayer

Shutter Type Global Shutter

Maximum Data Rate Master Clock

Full Resolution 752 x 480

Frame Rate 60 fps (at full resolution)

ADC Resolution 10-bit column-parallel

Responsivity 4.8 V/lux−sec (550 nm)

Dynamic Range >55 dB linear;

Supply Voltage 3.3 V ± 0.3 V (all supplies)

5.35 mm diagonal

pattern

27 Mp/s 27 MHz

>110 dB in HDR mode

Power Consumption <160 mW at maximum data rate

Operating Temperature –40°C to +105°C ambient

Packaging 52-ball IBGA, automotive-qualified;

(LVDS disabled); 120 μW standby power

wafer or die

ORDERING INFORMATION

Table 2. AVAILABLE PART NUMBERS

Part Number

MT9V023IA7XTC−DP VGA 1/3” GS CIS Dry Pack with Protective Film

MT9V023IA7XTC−DR VGA 1/3” GS CIS Dry Pack without Protective Film

MT9V023IA7XTC−TP VGA 1/3” GS CIS Tape & Reel with Protective Film

MT9V023IA7XTC−TR VGA 1/3” GS CIS Tape & Reel without Protective Film

MT9V023IA7XTM−DR VGA 1/3” GS CIS Dry Pack without Protective Film

MT9V023IA7XTR−TP VGA 1/3” GS CIS Tape & Reel with Protective Film

Product Description Orderable Product Attribute Description

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Active−Pixel

Sensor (APS)

Array

752H x 480V

Analog Processing

MT9V023

Control Register

Timing and Control

Serial Register I/O

VDD

LVDS

GND

BYPASS

_CLKIN

SER_

DATAOUT

SHFT_

CLKOUT

BYPASS

_CLKIN

ADCs

Slave Video LVDS In

(for stereo applications only)

Figure 1. Block Diagram

SER_

DATAOUT

SHFT_

CLKOUT

LVDS

GND

VDD LVDS

VDD

Digital Processing

Serial Video

LVDS Out

SYS−

DOUT0

CLK

PIXCLK

DOUT1

DGND

Parallel Video Data Out

DOUT2

DOUT4

AGND

DOUT3

VAAPIX

VAA

SER_

DATAIN

DOUT5

DOUT6

DOUT8

DOUT9

SER_

DATAIN

VDD

DOUT7

FRAME _VALID

LINE_

VALID

DGND

STLN_

OUT

EXPO−

SURE

SDATA

SCLK

STFRM_

OUT

ERROR

AGND

LED_ OUT

VAA

S_CTRL_

ADR0

RSVD

STAND−

RESET_

BAR

S_CTRL

_ADR1

Figure 2. 52-Ball IBGA Package

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MT9V023

BALL DESCRIPTIONS

Table 3. BALL DESCRIPTIONS

52-Ball IBA Numbers Symbol Type Description Note

H7 RSVD Input Connect to DGND. 1

D2 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative).

D1 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive).

C2 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential negative). Tie to

C1 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to

H3 EXPOSURE Input Rising edge starts exposure in snapshot and slave

H4 SCLK Input Two-wire serial interface clock. Connect to VDD with

H6 OE Input DOUT enable pad, active HIGH. 2

G7 S_CTRL_ADR0 Input Two-wire serial interface slave address select (see

H8 S_CTRL_ADR1 Input Two-wire serial interface slave address select (see

G8 RESET_BAR Input Asynchronous reset. All registers assume defaults.

F8 STANDBY Input Shut down sensor operation for power saving.

A5 SYSCLK Input Master clock (26.6 MHz; 13 MHz – 27 MHz).

G4 SDATA I/O Two-wire serial interface data. Connect to VDD with

G3 STLN_OUT I/O

G5 STFRM_OUT I/O

H2 LINE_VALID Output Asserted when DOUT data is valid.

G2 FRAME_VALID Output Asserted when DOUT data is valid.

E1 DOUT5 Output Parallel pixel data output 5.

F1 DOUT6 Output Parallel pixel data output 6.

F2 DOUT7 Output Parallel pixel data output 7.

G1 DOUT8 Output Parallel pixel data output 8

H1 DOUT9 Output Parallel pixel data output 9.

H5 ERROR Output Error detected. Directly connected to STEREO

G6 LED_OUT Output LED strobe output.

B7 DOUT4 Output Parallel pixel data output 4.

A8 DOUT3 Output Parallel pixel data output 3.

A7 DOUT2 Output Parallel pixel data output 2.

B6 DOUT1 Output Parallel pixel data output 1.

A6 DOUT0 Output Parallel pixel data output 0.

Tie to 1KΩ pull-up (to 3.3 V) in non-stereoscopy mode.

Tie to D

GND in non-stereoscopy mode.

1KΩ pull-up (to 3.3 V) in non-stereoscopy mode.

GND in non-stereoscopy mode.

modes.

1.5 K resistor even when no other two-wire serial interface peripheral is attached.

Table 6).

1.5 K resistor even when no other two-wire serial interface peripheral is attached.

Output in master mode−start line sync to drive slave chip in-phase; input in slave mode.

Output in master mode−start frame sync to drive a slave chip in-phase; input in slave mode.

ERROR FLAG.

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MT9V023

Table 3. BALL DESCRIPTIONS (continued)

52-Ball IBA Numbers NoteDescriptionTypeSymbol

B5 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this

B3 SHFT_CLKOUT_N Output Output shift CLK (differential negative).

B2 SHFT_CLKOUT_P Output Output shift CLK (differential positive).

A3 SER_DATAOUT_N Output Serial data out (differential negative).

A2 SER_DATAOUT_P Output Serial data out (differential positive).

B4, E2 VDD Supply Digital power 3.3 V.

C8, F7 VAA Supply Analog power 3.3 V.

B8 VAAPIX Supply Pixel power 3.3 V.

A1, A4 VDDLVDS Supply Dedicated power for LVDS pads.

B1, C3 LVDSGND Ground Dedicated GND for LVDS pads.

C6, F3 DGND Ground Digital GND.

C7, F6 AGND Ground Analog GND.

E7, E8, D7, D8 NC NC No connect. 3

1. Pin H7 (RSVD) must be tied to GND.

2. Output enable (OE) tri-states signals D

OUT0–DOUT9, LINE_VALID, FRAME_VALID, and PIXCLK.

3. No connect. These pins must be left floating for proper operation.

clock.

1.5K

Master Clock

10K

DDLVDS

SYSCLK

RESET_BAR

STANDBY from

Controller or

Digital GND

EXPOSURE

STANDBY

S_CTRL_ADR0

S_CTRL_ADR1

Two−Wire

Serial Interface

SCLK

DATA

RSVD

0.1 F

Note: LVDS signals are to be left floating.

Figure 3. Typical Configuration (Connection) − Parallel Output Mode

VDD

VAA VAAPIX

VDD VAA

LVDSGND

VAAPIX

OUT(9:0)

LINE_VALID

FRAME_VALID

PIXCLK

LED_OUT

ERROR

GNDDGND

To Controller

To LED output

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MT9V023

PIXEL DATA FORMAT

Pixel Array Structure

The MT9V023 pixel array is configured as 809 columns by 499 rows, shown in Figure 4. The dark pixels are optically black and are used internally to monitor black level. Of the left 52 columns, 36 are dark pixels used for row noise correction. Of the top 14 rows of pixels, two of the dark rows are used for black level correction. Also, three black rows from the top black rows can be read out by setting the Show Dark Rows bit in the Read Mode register; setting Show Dark Columns will display the 36 dark columns. There are 753 columns by 481 rows of optically active

2 barrier + 8 (2 + 4 addressed + 2) dark + 2 barrier + 2 light dummy

pixels. While the sensor’s format is 752 x 480, one additional active column and active row are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. This one pixel adjustment is always performed, for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Neither dummy pixels nor barrier pixels can be read out.

(0, 0)

active pixel

4.92 x 3.05mm Pixel Array 809 x 499 (753 x 481 active)

6.0 μm pixel

3 barrier + 38 (1 + 36 addressed + 1) dark + 9 barrier + 2 light dummy

2 barrier + 2 light dummy

Figure 4. Pixel Array Description

Column Readout Direction

Row Readout Direction

2 barrier + 2 light dummy

Active Pixel (0,0) Array Pixel (4,14)

light dummy pixel

dark pixel

barrier pixel

Figure 5. Pixel Color Pattern Detail (Top Right Corner)

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MT9V023

COLOR DEVICE LIMITATIONS

The color version of the MT9V023 does not support or offers reduced performance for the following functionalities.

Pixel Binning

Pixel binning is done on immediate neighbor pixels only, no facility is provided to skip pixels according to a Bayer pattern. Therefore, the result of binning combines pixels of different colors. See “Pixel Binning” for additional information.

Interlaced Readout

Interlaced readout yields one field consisting only of red and green pixels and another consisting only of blue and green pixels. This is due to the Bayer pattern of the CFA.

Automatic Black Level Calibration

When the color bit is set (R0x0F[1]=1), the sensor uses black level correction values from one green plane, which are applied to all colors. To use the calibration value based

on all dark pixels’ offset values, the color bit should be cleared.

Defective Pixel Correction

For Defective Pixel Correction to calculate replacement pixel values correctly, for color sensors the color bit must be set (R0x0F[1] = 1). However, the color bit also applies unequal offset to the color planes, and the results might not be acceptable for some applications.

Other Limiting Factors

Black level correction and row-wise noise correction are applied uniformly to each color. The row-wise noise correction algorithm does not work well in color sensors. Automatic exposure and gain control calculations are made based on all three colors, not just the green channel. High dynamic range does operate in color; however, ON Semiconductor strongly recommends limiting use to linear operation where good color fidelity is required.

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MT9V023

OUTPUT DATA FORMAT

The MT9V023 image data can be read out in a progressive scan or interlaced scan mode. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 6. The amount of horizontal and vertical blanking is

programmable through R0x05 and R0x06, respectively (R0xCD and R0xCE for context B). LV is HIGH during the shaded region of the figure. See “Output Data Timing” for the description of FV timing.

0,0 P0,1 P0,2

1,0 P1,1 P1,2

.....................................P

0,n−1P0,n

1,n−1P1,n

VALID IMAGE

m−1,0 Pm−1,1

m,0 Pm,1

.....................................P

m−1,n−1Pm−1,n

m,n−1Pm,n

00 00 00 ..................................... 00 00 00

VERTICAL BLANKING

00 00 00 ..................................... 00 00 00

00 00 00 .................. 00 00 00

HORIZONTAL

BLANKING

00 00 00 .................. 00 00 00

VERTICAL/HORIZONTAL

BLANKING

00 00 00 .................. 00 00 00

Figure 6. Spatial Illustration of Image Readout

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MT9V023

OUTPUT DATA TIMING

The data output of the MT9V023 is synchronized with the PIXCLK output. When LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIXCLK period.

LINE_VALID

PIXCLK

...

Valid Image DataBlanking Blanking

...

OUT(9:0)

(9:0)

Figure 7. Timing Example of Pixel Data

The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled, the PIXCLK is HIGH for one complete master clock master period and then LOW for one complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for two

FRAME_VALID

LINE_VALID

Number of master clocks

Figure 8. Row Timing and FRAME_VALID/LINE_VALID Signals

Table 4. FRAME TIME

Parameters

A Active data time Context A: R0x04

P1 Frame start blanking Context A: R0x05 - 23

P2 Frame end blanking 23 (fixed) 23 pixel clocks

Q Horizontal blanking Context A: R0x05

A+Q Row time Context A: R0x04 + R0x05

V Vertical blanking Context A: (R0x06) x (A + Q) + 4

Name Equation

P1 A QA QAP2

Context B: R0xCC

Context B: R0xCD - 23

Context B: R0xCD

Context B: R0xCC + R0xCD

Context B: (R0xCE) x (A + Q) + 4

(9:0)

...

n−1

(9:0)

complete master clock periods and then LOW for two complete master clock periods. It is continuously enabled, even during the blanking period. Setting R0x72 bit[4] = 1 causes the MT9V023 to invert the polarity of the PIXCLK.

The parameters P1, A, Q, and P2 in Figure 8 are defined

in Table 4.

...

Default Timing at

752 pixel clocks = 752 master = 28.2 μs

71 pixel clocks = 71master = 2.66 μs

= 23 master = 0.86 μs

94 pixel clocks = 94 master = 3.52 μs

846 pixel clocks = 846 master = 31.72 μs

38,074 pixel clocks = 38,074 master = 1.43 ms

26.66 MHz

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MT9V023

Table 4. FRAME TIME (continued)

Parameters

Nrows x (A + Q) Frame valid time Context A: (R0x03) × (A + Q)

Context B: (R0xCB) x (A + Q)

F Total frame time V + (Nrows x (A + Q)) 444,154 pixel clocks

Default Timing at

EquationName

26.66 MHz

406,080 pixel clocks = 406,080 master = 15.23 ms

= 444,154 master = 16.66 ms

Sensor timing is shown above in terms of pixel clock and master clock cycles (refer to Figure 7). The recommended master clock frequency is 26.66 MHz. The vertical blanking and the total frame time equations assume that the integration time (Coarse Shutter Width plus Fine Shutter Width) is less than the number of active rows plus the blanking rows minus the overhead rows:

Table 5. In this example it is assumed that the Coarse Shutter Width Control is programmed with 523 rows, and the Fine Shutter Width Total is zero.

For Simultaneous mode, if the exposure time registers (Coarse Shutter Width Total plus Fine Shutter Width Total) exceed the total readout time, then the vertical blanking time is internally extended automatically to adjust for the additional integration time required. This extended value is

Window Height ) Vertical Blanking * 2

(eq.1)

not written back to the vertical blanking registers. The Vertical Blank register can be used to adjust frame-to-frame

If this is not the case, the number of integration rows must

be used instead to determine the frame time, as shown in

Table 5. FRAME TIME−LONG INTEGRATION TIME

Parameter Name

V’

F’

1. The MT9V023 uses column parallel analog−digital converters, thus short row timing is not possible. The minimum total row time is 690 columns (horizontal width + horizontal blanking). The minimum horizontal blanking is 61. When the window width is set below 627, horizontal blanking must be increased.

Vertical blanking (long integration time)

Total frame time (long integration time)

Context A: (R0x0B + 2 − R0x03) y (A + Q) + R0xD5 + 4

Context B: (R0xD2 + 2 − R0xCB) x (A + Q) + R0xD8 + 4

Context A: (R0x0B + 2) y (A + Q) + R0xD5 +4 Context B: (R0xD2 + 2) x (A + Q) + R0xD8 +4

readout time. This register does not affect the exposure time but it may extend the readout time.

(Number of Master Clock Cycles)

Equation

Default Timing

at 26.66 MHz

38,074 pixel clocks

= 38,074 master = 1.43 ms

444,154 pixel clocks

= 444,154 master = 16.66 ms

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MT9V023

SERIAL BUS DESCRIPTION

Registers are written to and read from the MT9V023 through the two-wire serial interface bus. The MT9V023 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0 and 0xB8) determined by the S_CTRL_ADR0 and S_CTRL_ADR1 input pins. Data is transferred into the MT9V023 and out through the serial data (S S

DATA line is pulled up to VDD off-chip by a 1.5KΩ resistor.

Either the slave or master device can pull the S down−the serial interface protocol determines which device is allowed to pull the S

DATA line down at any given time. The

registers are 16-bit wide, and can be accessed through 16− or 8−bit two−wire serial interface sequences.

Protocol

The two-wire serial interface defines several different transmission codes, as shown in the following sequence:

1. a start bit

2. the slave device 8-bit address

3. a(n) (no) acknowledge bit

4. an 8-bit message

5. a stop bit

Start Bit

The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH.

Slave Address

The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. As indicated above, the MT9V023 allows four possible slave addresses determined by the two input pins, S_CTRL_ADR0 and S_CTRL_ADR1.

Acknowledge Bit

The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse.

No-Acknowledge Bit

The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.

DATA) line. The

DATA line

Stop Bit

The stop bit is defined as a LOW-to-HIGH transition of

the data line while the clock line is HIGH.

Sequence

A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device’s 8-bit address. The last bit of the address determines if the request is a read or a write, where a “0” indicates a WRITE and a “1” indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master.

If the request was a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9V023 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit.

A typical READ sequence is executed as follows. First the master sends the write mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V023 allows for 8-bit data transfers through the two-wire serial interface by writing (or reading) the most significant 8 bits to the register and then writing (or reading) the least significant 8 bits to Byte-Wise Address register (0x0F0).

Bus Idle State

The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits.

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MT9V023

Table 6. SLAVE ADDRESS MODES

{S_CTRL_ADR1, S_CTRL_ADR0} Slave Address Write/Read Mode

0x90 Write

0x91 Read

0x98 Write

0x99 Read

0xB0 Write

0xB1 Read

0xB8 Write

0xB9 Read

Data Bit Transfer

One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of

the serial clock−it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.

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MT9V023

TWO-WIRE SERIAL INTERFACE SAMPLE READ AND WRITE SEQUENCES

16-Bit Write Sequence

A typical write sequence for writing 16 bits to a register is shown in Figure 9. A start bit given by the master, followed by the write address, starts the sequence. The image sensor then gives an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit the image sensor gives an acknowledge bit.

SCLK

SDATA

All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit.

0xBA ADDR

START ACK

Reg0x09

Figure 9. Timing Diagram Showing a WRITE to Reg0x09 with the Value 0x0284

16-Bit Read Sequence

A typical read sequence is shown in Figure 10. First the master has to write the register address, as in a write sequence. Then a start bit and the read address specifies that a read is about to happen from the register. The master then

SCLK

DATA

0xBA ADDR 0xB9 ADDR 0000 0010

START ACK

Reg0x09

ACK ACK ACK

Figure 10. Timing Diagram Showing a READ from Reg0x09, Returned Value 0x0284

8-Bit Write Sequence

To be able to write 1 byte at a time to the register a special register address is added. The 8-bit write is done by first writing the upper 8 bits to the desired register and then writing the lower 8 bits to the Bytewise Address register

0000 0010

ACK ACK ACK

1000 0100

clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

1000 0100

NACK

(R0xF0). The register is not updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 11, a typical sequence for 8-bit writing is shown. The second byte is written to the Bytewise register (R0xF0).

STOP

CLK

ATA

0xB8 ADDR

Figure 11. Timing Diagram Showing a Bytewise Write to R0x09 with the Value 0x0284

R0x09

0000 0010 1000 0100

ACKSTART

0xB8 ADDR

START

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R0xF0

ACKACKACKACK

STO

ACK

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