Datasheet MJF15030, MJF15030G, MJF15031, MJF15031G Datasheet (ON Semiconductor)

MJF15030 (NPN),
MJF15031 (PNP)

Complementary Power
Transistors

For Isolated Package Applications

Designed for general−purpose amplifier and switching applications,

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where the mounting surface of the device is required to be electrically
isolated from the heatsink or chassis.

Features

• Electrically Similar to the Popular MJE15030 and MJE15031

• 150 V

CEO(sus)

COMPLEMENTARY SILICON

POWER TRANSISTORS

8 AMPERES

150 VOLTS, 36 WATTS

• 8 A Rated Collector Current

• No Isolating Washers Required

• Reduced System Cost

• High Current Gain−Bandwidth Product −

fT= 30 MHz (Min) @ I

= 500 mAdc

C

• UL Recognized, File #E69369, to 3500 V

RMS

Isolation

MARKING
DIAGRAM

• Pb−Free Packages are Available*

MAXIMUM RATINGS

Rating

Collector−Emitter Voltage

Collector−Base Voltage

Emitter−Base Voltage

RMS Isolation Voltage (Note 1)

(t = 0.3 sec, R.H. ≤ 30%, TA = 25_C)
Per Figure 11

Collector Current − Continuous

− Peak

Base Current

Total Power Dissipation (Note 2) @ TC = 25_C
Derate above 25_C

Total Power Dissipation @ TA = 25_C
Derate above 25_C

Operating and Storage Temperature Range

Symbol

V

CEO

V

CB

V

EB

V

ISOL

I

C

I

B

P

D

P

D

TJ, T

stg

Value

150

150

5

4500

8

16

2

36

0.016

2.0

0.016

–65 to +150

Unit

Vdc

Vdc

Vdc

V

RMS

Adc

Adc

W

W/_C

W

W/_C

_C

1

2

THERMAL CHARACTERISTICS

Characteristic

Thermal Resistance, Junction−to−Ambient

Thermal Resistance, Junction−to−Case (Note 2)

Lead Temperature for Soldering Purposes

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Proper strike and creepage distance must be provided.

2. Measurement made with thermocouple contacting the bottom insulated
surface (in a location beneath the die), the devices mounted on a heatsink with
thermal grease and a mounting torque of ≥ 6 in. lbs.

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

Symbol

R

q

JA

R

q

JC

T

L

Max

62.5

3.5

260

Unit

_C/W

_C/W

_C

Device Package Shipping

MJF15030 TO−220 FULLPACK

MJF15030G TO−220 FULLPACK

MJF15031 50 Units/Rail

MJF15031G 50 Units/Rail

TO−220 FULLPACK

3

MJF1503x = Specific Device Code

G=Pb−Free Package
A = Assembly Location
Y = Year
WW = Work Week

CASE 221D

STYLE 2

x = 0 or 1

ORDERING INFORMATION

(Pb−Free)

TO−220 FULLPACK

TO−220 FULLPACK

(Pb−Free)

MJF1503xG

AYW W

50 Units/Rail

50 Units/Rail

© Semiconductor Components Industries, LLC, 2008

July, 2008 − Rev. 6

1 Publication Order Number:

MJF15030/D

MJF15030 (NPN), MJF15031 (PNP)

ELECTRICAL CHARACTERISTICS (T

= 25_C unless otherwise noted)

C

Characteristic

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 3)

(IC = 10 mAdc, IB = 0)

Collector Cutoff Current

(V

= 150 Vdc, IB = 0)

CE

Collector Cutoff Current

(VCB = 150 Vdc, IE = 0)

Emitter Cutoff Current

(VBE = 5 Vdc, IC = 0)

ON CHARACTERISTICS (Note 3)

DC Current Gain (IC = 0.1 Adc, VCE = 2 Vdc)

(IC = 2 Adc, VCE = 2 Vdc)
(IC = 3 Adc, VCE = 2 Vdc)
(IC = 4 Adc, VCE = 2 Vdc)

DC Current Gain Linearity

(VCE from 2 V to 20 V, IC from 0.1 A to 3 A) (NPN to PNP)

Collector−Emitter Saturation Voltage

(IC = 1 Adc, IB = 0.1 Adc)

Base−Emitter On Voltage

(IC = 1 Adc, VCE = 2 Vdc)

DYNAMIC CHARACTERISTICS

Current Gain − Bandwidth Product (Note 4)

(IC = 500 mAdc, VCE = 10 Vdc, f

= 10 MHz)

test

3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.

4. fT = ⎪hfe⎪• f

test

.

Symbol

V

CEO(sus)

I

CEO

I

CBO

I

EBO

h

FE

h

FE

V

CE(sat)

V

BE(on)

f

T

Min

150

−

−

−

40
40
40
20

−

−

30

Typ

2
3

Max

−

10

10

10

−

−

−

−

0.5

1

−

Unit

Vdc

mAdc

mAdc

mAdc

−

Vdc

Vdc

MHz

1

0.5

0.3

0.2

0.1

0.05

0.03

0.02

0.01

0.3

0.1 0.2 20 200 2K2

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

0.5 10 30 50 100 300 500 1K 3K 5K

SINGLE PULSE
R

= r(t) R

q

JC(t)

T

J(pk)

- TC = P

q

(pk)

JC

R

(t)

q

JC

153 10K

t, TIME (ms)

Figure 1. Thermal Response

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2

MJF15030 (NPN), MJF15031 (PNP)

20

10

5
3

2

1

0.5

0.3

0.2

0.1

, COLLECTOR CURRENT (AMP)

C

I

0.05

0.03

0.02

dc

WIREBOND LIMIT
THERMAL LIMIT
SECONDARY BREAKDOWN
LIMIT @ TC = 25°C

5 200

3

V

CE

10 30 50 70

, COLLECTOR-EMITTER VOLTAGE (VOLTS)

100 ms

5 ms

Figure 2. Forward Bias Safe Operating Area

8

5

3

IC/IB = 10

2

, COLLECTOR CURRENT (AMP)

C

I

TC = 25°C

1

0

100

0 120 140

110

VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

130 150

V

BE(off)

5 V
3 V

1.5 V
0 V

= 9 V

There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC − V

CE

limits of the transistor that must be observed for reliable
operation, i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.

The data of Figures 2 and 3 is based on T

J(pk)

= 150_C;
TC is variable depending on conditions. Second breakdown
pulse limits are valid for duty cycles to 10% provided T
< 150_C. T

may be calculated from the data in

J(pk)

J(pk)

Figure 1. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the

1002720

150

limitations imposed by second breakdown.

1000

500

200

100

50

30

20

10

1.5

53

VR, REVERSE VOLTAGE (VOLTS)

Cib (NPN)

Cib (PNP)

10

7

30 50 100

Cob (PNP)

Cob (NPN)

150

Figure 3. Reverse Bias Switching Safe

Operating Area

100

50

30

20

10

, SMALL-SIGNAL CURRENT GAIN

fe

h

5

0.5 5 1013

0.7

VCE = 10 V
IC = 0.5 A
TC = 25°C

27

f, FREQUENCY (MHz)

NPN

Figure 5. Small−Signal Current Gain Figure 6. Current Gain — Bandwidth Product

PNP

Figure 4. Capacitances

100

90

60

50

20

10

0

, CURRENT GAIN — BANDWIDTH PRODUCT (MHz) C, CAPACITANCE (pF)

T

f

0.1 5 100.5 2

0.2

IC, COLLECTOR CURRENT (AMP)

(PNP)

(NPN)

1

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3

MJF15030 (NPN), MJF15031 (PNP)

DC CURRENT GAIN

1K

500

200

150

100

70
50

, DC CURRENT GAIN

FE

h

30

20

10

TJ = 150°C

TJ = 25°C

TJ = -55°C

15100.1

0.50.2

IC, COLLECTOR CURRENT (AMP)

2

VCE = 2 V

1K

500

200

100

, DC CURRENT GAIN

FE

h

TJ = 150°C

TJ = 25°C

50

20

10

TJ = -55°C

IC, COLLECTOR CURRENT (AMP)

Figure 7a. MJF15030 NPN Figure 7b. MJF15031 PNP

“ON” VOLTAGE

TJ = 25°C

1.6

1.2

1

V

@ IC/IB = 10

BE(sat)

V, VOLTAGE (VOLTS)

0.6

V

0.2

0.1 5 100.5 2

CE(sat)

0.2

V

BE(on)

@ IC/IB = 20

IC, COLLECTOR CURRENT (AMP)

@ VCE = 2 V

IC/IB = 10

1

1.8

1.4

1

0.8

V

@ IC/IB = 10

BE(sat)

V, VOLTAGE (VOLTS)

V

@ IC/IB = 20

CE(sat)

0.4

V

@ IC/IB = 20

BE(sat)

0

0.1 5 100.5 2

0.2

IC, COLLECTOR CURRENT (AMP)

VCE = 2 V

0.50.2

15100.1 2

IC/IB = 10

1

Figure 8a. MJF15030 NPN

1

VCC = 80 V

0.5

0.2

0.1

t, TIME (s)μ

0.05

0.03

0.02

0.01

0.2 0.5 10

0.1 1 5

IC, COLLECTOR CURRENT (AMP)

IC/IB = 10
TJ = 25°C

tr (PNP)

tr (NPN)

Figure 9. Turn−On Times Figure 10. Turn−Off Times

2

td (NPN, PNP)

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Figure 8b. MJF15031 PNP

10

5

3

2

1

t, TIME (s)μ

0.5

0.2

tf (NPN)

0.1

0.1 5 100.5 20.2 1

4

ts (PNP)

tf (PNP)

0.3

IC, COLLECTOR CURRENT (AMP)

VCC = 80 V
IC/IB = 10, IB1 = I
ts (NPN) TJ = 25°C

B2

MJF15030 (NPN), MJF15031 (PNP)

TEST CONDITIONS FOR ISOLATION TESTS*

FULLY ISOLATED PACKAGE

LEADS

HEATSINK

0.110, MIN

Figure 11. Mounting Position

*Measurement made between leads and heatsink with all leads shorted together.

MOUNTING INFORMATION

4-40 SCREW

PLAIN WASHER

HEATSINK

COMPRESSION WASHER

NUT

CLIP

HEATSINK

Figure 12. Typical Mounting Techniques*

Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw torque of 6 to
8 in.lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a constant pressure on the package
over time and during large temperature excursions.

Destructive laboratory tests show that using a hex head 4−40 screw, without washers, and applying a torque in excess of 20 in.lbs will cause the
plastic to crack around the mounting hole, resulting in a loss of isolation capability.

Additional tests on slotted 4−40 screws indicate that the screw slot fails between 15 to 20 in.lbs without adversely affecting the package. However,
in order to positively ensure the package integrity of the fully isolated device, ON Semiconductor does not recommend exceeding 10 in.lbs of mount­ing torque under any mounting conditions.

** For more information about mounting power semiconductors see Application Note AN1040.

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5

MJF15030 (NPN), MJF15031 (PNP)

l

PACKAGE DIMENSIONS

TO−220 FULLPAK

CASE 221D−03

ISSUE J

SEATING

−T−

PLANE

F

−B−

Q

C

S

U

A

123

H

G
N

−Y−

J

R

K

L

D

3 PL

M

M

0.25 (0.010) Y

B

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH

3. 221D-01 THRU 221D-02 OBSOLETE, NEW
STANDARD 221D-03.

INCHES

DIMAMIN MAX MIN MAX

0.617 0.635 15.67 16.12

B 0.392 0.419 9.96 10.63
C 0.177 0.193 4.50 4.90
D 0.024 0.039 0.60 1.00

F 0.116 0.129 2.95 3.28
G 0.100 BSC 2.54 BSC
H 0.118 0.135 3.00 3.43

J 0.018 0.025 0.45 0.63
K 0.503 0.541 12.78 13.73

L 0.048 0.058 1.23 1.47
N 0.200 BSC 5.08 BSC
Q 0.122 0.138 3.10 3.50
R 0.099 0.117 2.51 2.96

S 0.092 0.113 2.34 2.87
U 0.239 0.271 6.06 6.88

STYLE 2:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

MILLIMETERS

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MJF15030/D

6