Designed for general purpose power and switching such as output or
driver stages in applications such as switching regulators, converters,
and power amplifiers.
Features
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
• Straight Lead Version in Plastic Sleeves (“−1” Suffix)
• Electrically Similar to Popular TIP31 and TIP32 Series
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
R
q
JC
R
q
JA
100Vdc
100Vdc
5Vdc
2
4
50mAdc
20
0.16
1.75
0.014
−65 to + 150°C
6.25°C/W
71.4°C/W
Adc
W
W/°C
W
W/°C
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SILICON
POWER TRANSISTORS
2 AMPERES
100 VOLTS, 20 WATTS
MARKING
DIAGRAMS
4
YWW
2
1
3
DPAK
CASE 369C
4
1
2
3
DPAK−3
CASE 369D
Y= Year
WW= Work Week
x= 2 or 7
G= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
*These ratings are applicable when surface mounted on the minimum pad sizes recommended.
RB & RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
D1, MUST BE FAST RECOVERY TYPE, e.g.:
V
CC
−30 V
4
1N5825 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
V
2
APPROX
+8 V
0
V
1
51
APPROX
−12 V
tr, tf ≤ 10 ns
DUTY CYCLE = 1%
25 ms
FOR td AND tr, D1 IS DISCONNECTED
AND V2 = 0
FOR NPN TEST CIRCUIT REVERSE ALL POLARITIES.
R
D
B
1
+ 4 V
≈ 8 k
TUT
≈ 60
R
C
SCOPE
2
1
0.8
t, TIME (s)μ
0.6
0.4
0.2
0.040.240.1
PNP
NPN
0.06
IC, COLLECTOR CURRENT (AMP)
ÎÎ
−
Î
2.8
Vdc
ÎÎ
MHz
25
ÎÎ
−
Î
ÎÎ
pF
−
ÎÎ
−
VCC = 30 V
t
s
IC/IB = 250
0.42
200
Î
100
0.61
t
f
td @ V
ÎÎ
IB1 = I
B2
TJ = 25°C
t
= 0 V
BE(off)
r
Figure 1. Switching Times Test CircuitFigure 2. Switching Times
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2
1
ACTIVE−REGION SAFE−OPERATING AREA
0.7
0.5
0.3
0.2
0.1
0.07
0.05
r(t), EFFECTIVE TRANSIENT
0.03
0.02
THERMAL RESISTANCE (NORMALIZED)
0.01
0.01
10
7
5
3
2
1
0.7
0.5
0.3
0.2
0.1
, COLLECTOR CURRENT (AMP)
C
I
2
MJD112 (NPN) MJD117 (PNP)
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
0.02 0.03 0.050.10.2 0.30.5123510203050100200 300500
t, TIME OR PULSE WIDTH (ms)
R
= r(t) R
q
JC(t)
R
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
T
J(pk)
q
= 6.25°C/W
− TC = P
(pk) qJC(t)
JC
1
Figure 3. Thermal Response
TAT
C
25
2.5
100ms
500ms
1ms
BONDING WIRE LIMITED
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
TJ = 150°C
CURVES APPLY BELOW RATED V
5203
10730
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
5ms
dc
CEO
50 70200
100
1.5
0.5
, POWER DISSIPATION (WATTS)
D
P
20
2
15
10
1
5
0
0
25
SURFACE
MOUNT
507510012515
P
(pk)
t
1
DUTY CYCLE, D = t1/t
T
TA
T, TEMPERATURE (°C)
C
t
2
2
1000
Figure 4. Maximum Rated Forward Biased
Safe Operating Area
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
limits of the transistor that must be observed for reliable
C
− V
CE
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figures 5 and 6 is based on T
= 150_C; T
J(pk)
is variable depending on conditions. Second breakdown
pulse limits are valid for duty cycles to 10% provided
T
< 150_C. T
J(pk)
may be calculated from the data in
J(pk)
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
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Figure 5. Power Derating
200
100
70
C, CAPACITANCE (pF)
50
30
20
10
0.04
C
ib
PNP
NPN
0.12620
VR, REVERSE VOLTAGE (VOLTS)
141040
0.60.40.20.06
C
TC = 25°C
C
ob
Figure 6. Capacitance
3
MJD112 (NPN) MJD117 (PNP)
TYPICAL ELECTRICAL CHARACTERISTICS
NPN MJD112PNP MJD117
, DC CURRENT GAIN
FE
h
6 k
4 k
3 k
2 k
1 k
800
600
400
300
0.04
0.060.2
3.4
3
IC =
0.5 A
2.6
2.2
TJ = 125°C
VCE = 3 V
25°C
−55 °C
2 A
0.41
4 A
0.10.6
IC, COLLECTOR CURRENT (AMP)
1 A
240.04
Figure 7. DC Current Gain
TJ = 125°C
, DC CURRENT GAIN
FE
h
6 k
4 k
3 k
2 k
1 k
800
600
400
300
0.060.2
3.4
3
IC =
2.6
0.5 A
2.2
TC = 125°C
25°C
−55 °C
0.10.6
IC, COLLECTOR CURRENT (AMP)
1 A4 A2 A
0.41
VCE = 3 V
24
TJ = 125°C
1.8
1.4
1
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
CE
0.6
V
0.10.20.51025
2.2
TJ = 25°C
1.8
V
@ IC/IB = 250
BE(sat)
1.4
1
V
V, VOLTAGE (VOLTS)
0.6
0.2
0.04
CE(sat)
0.060.220.10.60.4140.04
1
IB, BASE CURRENT (mA)
@ IC/IB = 250
IC, COLLECTOR CURRENT (AMP)
1.8
1.4
1
, COLLECTOR−EMITTER VOLTAGE (VOLTS)
CE
0.6
2050100
V
0.10.20.510251
Figure 8. Collector Saturation Region
2.2
TJ = 25°C
1.8
V
@ IC/IB = 250
VBE @ VCE = 3 V
V, VOLTAGE (VOLTS)
BE(sat)
1.4
1
V
@ IC/IB = 250
CE(sat)
0.6
0.2
0.060.220.10.60.414
Figure 9. “On Voltages
2050100
IB, BASE CURRENT (mA)
VBE @ VCE = 3 V
IC, COLLECTOR CURRENT (AMP)
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4
MJD112 (NPN) MJD117 (PNP)
NPN MJD112PNP MJD117
+0.8
+0.8
*APPLIED FOR IC/IB < hFE/3
0
−0.8
−1.6
−2.4
*qVC FOR V
CE(sat)
25°C TO 150°C
−0.8
−1.6
−2.4
−55 °C TO 25°C
−3.2
qVC FOR V
−4
, TEMPERATURE COEFFICIENTS (mV/C)°θ
V
−4.8
0.04
0.060.2
BE
0.10.6
25°C TO 150°C
−55 °C TO 25°C
0.41
24
−3.2
−4
, TEMPERATURE COEFFICIENTS (mV/C)°θ
V
−4.8
IC, COLLECTOR CURRENT (AMP)
Figure 10. Temperature Coefficients
5
10
REVERSEFORWARD
4
10
3
10
VCE = 30 V
10
10
10
*APPLIES FOR IC/IB < hFE/3
0
25°C TO 150°C
*qVC FOR V
CE(sat)
−55 °C TO 25°C
25°C TO 150°C
qVB FOR V
0.04
0.060.20.10.60.4124
BE
−55 °C TO 25°C
IC, COLLECTOR CURRENT (AMP)
5
REVERSEFORWARD
4
3
VCE = 30 V
2
10
TJ = 150°C
1
10
, COLLECTOR CURRENT (A)μI
C
0
10
−1
10
−0.6−0.2+0.8+1 +1.2 +1.4
100°C
25°C
0−0.4
+0.2 +0.4 +0.6
VBE, BASE−EMITTER VOLTAGE (VOLTS)
Figure 11. Collector Cut−Off Region
PNP
BASE
≈ 8 k≈ 120
COLLECTOR
2
10
TJ = 150°C
1
10
, COLLECTOR CURRENT (A)μI
C
0
10
−1
10
+0.6+0.2−0.8−1−1.2 −1.4
100°C
25°C
0+0.4
−0.2 −0.4 −0.6
VBE, BASE−EMITTER VOLTAGE (VOLTS)
NPN
COLLECTOR
BASE
≈ 8 k≈ 120
EMITTER
Figure 12. Darlington Schematic
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5
EMITTER
MJD112 (NPN) MJD117 (PNP)
ORDERING INFORMATION
DevicePackage TypePackageShipping
MJD112DPAK
MJD112GDPAK
MJD112−001DPAK−3
MJD112−1GDPAK−3
MJD112RLDPAK
MJD112RLGDPAK
MJD112T4DPAK
MJD112T4GDPAK
MJD117DPAK
MJD117GDPAK
MJD117−001DPAK−3
MJD117−1GDPAK−3
MJD117T4DPAK
MJD117T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
(Pb−Free)
DPAK
(Pb−Free)
369C
75 Units / Rail
369D
1800 Tape & Reel
369C
369D
369C2500 Tape & Reel
2500 Tape & Reel
75 Units / Rail
†
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6
MJD112 (NPN) MJD117 (PNP)
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
SEATING
−T−
PLANE
B
V
S
R
4
A
123
K
F
L
D
2 PL
G
0.13 (0.005)T
C
E
Z
U
J
H
M
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMIN MAX
A 0.235 0.2455.976.22
B 0.250 0.2656.356.73
C 0.086 0.0942.192.38
D 0.027 0.0350.690.88
E 0.018 0.0230.460.58
F 0.037 0.0450.941.14
G0.180 BSC4.58 BSC
H 0.034 0.0400.871.01
J 0.018 0.0230.460.58
K 0.102 0.1142.602.89
L0.090 BSC2.29 BSC
R 0.180 0.2154.575.45
S 0.025 0.0400.631.01
U 0.020−−−0.51−−−
V 0.035 0.0500.891.27
Z 0.155−−−3.93−−−
MILLIMETERSINCHES
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.101
3.0
0.118
5.80
0.228
1.6
0.063
SCALE 3:1
6.172
0.243
ǒ
inches
mm
Ǔ
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MJD112 (NPN) MJD117 (PNP)
PACKAGE DIMENSIONS
DPAK−3
CASE 369D−01
ISSUE B
V
S
−T−
SEATING
PLANE
F
B
R
4
123
G
A
K
D 3 PL
0.13 (0.005)T
C
E
J
H
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMIN MAX
Z
A 0.235 0.2455.976.35
B 0.250 0.2656.356.73
C 0.086 0.0942.192.38
D 0.027 0.0350.690.88
E 0.018 0.0230.460.58
F 0.037 0.0450.941.14
0.090 BSC2.29 BSC
G
H 0.034 0.0400.871.01
J 0.018 0.0230.460.58
K 0.350 0.3808.899.65
R 0.180 0.2154.455.45
S 0.025 0.0400.631.01
V 0.035 0.0500.891.27
Z 0.155−−−3.93−−−
MILLIMETERSINCHES
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
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Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MJD112/D
8
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