MG2040, SZMG2040
ESD Protection Diodes
Low Capacitance ESD Protection for
High Speed Video Interface
The MG2040 ESD protection diode is designed specifically to
protect HDMI and Display Port with full functionality ESD protection
and back drive current protection for V
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance for the high speed TMDS
lines.
Features
• Full Function HDMI / Display Port Solution
• Single Connect, Flow through Routing for TMDS Lines
• Low Capacitance (0.35 pF Typical, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 Level 4 (±8 kV Contact)
• UL Flammability Rating of 94 V−0
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• This is a Pb−Free Device
Typical Applications
• HDMI
• Display Port
line. Ultra−low capacitance
CC
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MARKING
DIAGRAM
18
UDFN18
CASE 517CP
1
2040 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device Package Shipping
MG2040MUTAG UDFN18
SZMG2040MUTAG UDFN18
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
(Pb−Free)
(Pb−Free)
2040MG
G
3000 / Tape &
Reel
3000 / Tape &
Reel
MAXIMUM RATINGS (T
Rating
Operating Junction Temperature Range T
Storage Temperature Range T
Lead Solder Temperature −
Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
= 25°C unless otherwise noted)
J
Symbol Value Unit
J
stg
T
L
ESD
ESD
−55 to +125 °C
−55 to +150 °C
260 °C
±15
±15
kV
kV
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2014
October, 2017 − Rev. 5
1 Publication Order Number:
MG2040/D
MG2040, SZMG2040
Pin 1 Pin 2 Pin 3
Pin 4 Pin 5 Pin 6
Note: Common GND – Only Minimum of 1 GND connection required
Pin 7 Pin 8 Pin 9
Center Pins, Pin 12, 14, 16, 18
=
Pin 10 Pin 11 Pin 13 Pin 15 Pin 17
Figure 1. Pin Schematic
I/O
I/O
I/O
1
2
GND
3
GND
18
I/O
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
5
6
7
8
9
10
11
GND
GND
16
GND
15
I/O
14
GND
13
I/O
12
GND
Figure 2. Pin Configuration
Note: Pins 12, 14, 16, 18 and center pins are connected internally as a common ground.
Only minimum of one pin needs to be connected to ground for functionality of all pins.
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2
MG2040, SZMG2040
RWM
BR
R
C
C
V
C
J
= 25°C unless otherwise specified)
A
I/O Pin to GND (Note 1) 5.0 V
IT = 1 mA, I/O Pin to GND 5.5 V
V
= 5 V, I/O Pin to GND 1.0
RWM
IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)
IEC61000−4−2, ±8 kV Contact See Figures 3 and 4 V
IPP = 8 A
I
= 16 A
PP
I
= −8 A
PP
= −16 A
I
PP
11.4
15.3
−4.6
−8.1
VR = 0 V, f = 1 MHz between I/O Pins 0.15 0.20
ELECTRICAL CHARACTERISTICS (T
Parameter
Reverse Working Voltage V
Breakdown Voltage V
Reverse Leakage Current I
Clamping Voltage (Note 1) V
Clamping Voltage (Note 2) V
Clamping Voltage
TLP (Note 3)
See Figures 8 through 11
Junction Capacitance C
Symbol Conditions Min Typ Max Unit
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.35 0.42
Junction Capacitance
Difference
DC
VR = 0 V, f = 1 MHz between I/O Pins 0.02
J
VR = 0 V, f = 1 MHz between I/O Pins and GND 0.04
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
= 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
0
90
80
0
70
60
−10
50
40
30
VOLTAGE (V)
20
10
−20
−30
VOLTAGE (V)
−40
0
−10
−20 0 20 40 60 80 100 120 140
−50
−20 0 20 40 60 80 100 120 140
TIME (ns) TIME (ns)
Figure 3. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 4. IEC61000−4−2 −8 KV Contact
Clamping Voltage
mA
10 V
pF
pF
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3
MG2040, SZMG2040
IEC 61000−4−2 Spec.
Test Volt-
Level
age (kV)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
ESD Gun
First Peak
Current
(A)
Current at
30 ns (A)
Device
Under
Test
50 W
Cable
IEC61000−4−2 Waveform
I
peak
Current at
60 ns (A)
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 5. IEC61000−4−2 Spec
Oscilloscope
50 W
tP = 0.7 ns to 1 ns
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
100
t
r
90
80
70
60
50
40
30
20
% OF PEAK PULSE CURRENT
10
0
020406080
PEAK VALUE I
t
P
Figure 7. 8 x 20 ms Pulse Waveform
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
@ 8 ms
RSM
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE I
t, TIME (ms)
/2 @ 20 ms
RSM
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4
MG2040, SZMG2040
22
20
18
16
14
12
10
8
CURRENT (A)
6
4
2
0
0 2 4 6 8 10 12 14 16 18
VOLTAGE (V)
Figure 8. Positive TLP I−V Curve Figure 9. Negative TLP I−V Curve
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 10. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 11 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
−22
−20
−18
−16
−14
−12
−10
−8
CURRENT (A)
−6
−4
−2
0
VOLTAGE (V)
L
Attenuator
S
50 W Coax
Cable
÷
50 W Coax
Cable
10 MW
V
C
Figure 10. Simplified Schematic of a Typical TLP
System
I
M
V
M
Oscilloscope
−18−16−14−12−10−8−6−4−20
DUT
Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
MG2040, SZMG2040
With MG2040Without ESD
Figure 12. HDMI1.4 Eye Diagram with and without MG2040. 3.4 Gb/s, 400 mV
4
PP
2
0
−2
−4
−6
S21 INSERTION LOSS (dB)
−8
−10
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
FREQUENCY (Hz)
MG2040
IO−GND
Figure 13. MG2040 Insertion Loss
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6
MG2040
MG2040, SZMG2040
HDMI Type−A
Connector
D2+
GND
D2−
D1+
GND
D1−
D0+
GND
D0−
CLK+
GND
CLK−
CEC
N/C (or HEC_DAT – HDMI1.4)
HPD (and HEC_DAT – HDMI1.4)
Figure 14. HDMI Layout Diagram
SCL
SDA
GND
5V
Black = Top layer
Red = other layer
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN18, 5.5x1.5, 0.5P/0.75P
18
1
SCALE 2:1
B
11
1218
0.75
PITCH
A
D2
18X
E
A
(A3)
A1
C
E2
L
b
M
0.10 B
M
0.05ACC
18X
0.50
REFERENCE
2X
2X
NOTE 4
DETAIL A
PIN ONE
D
0.10 C
0.10 C
TOP VIEW
DETAIL B
0.05 C
0.10 C
SIDE VIEW
eA
1
DETAIL C
eB
eC
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.13
3X
0.50
DETAIL A
OPTIONAL
CONSTRUCTION
SEATING
PLANE
NOTE 3
CASE 517CP
ISSUE A
LL2
D3
DETAIL B
CONSTRUCTION
NOTE 5
END VIEW
DETAIL C
MOLD CMPDEXPOSED Cu
OPTIONAL
DATE 07 FEB 2013
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.10 AND 0.20 MM FROM TERMINAL TIP.
D3
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. EXPOSED ENDS OF TERMINALS ARE
ELECTRICALLY ACTIVE.
MILLIMETERS
DIM MIN MAX
A 0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b 0.15 0.25
D 5.50 BSC
D2 0.35 0.45
0.10 REF
D3
E 1.50 BSC
E2 0.35 0.45
eA 0.50 BSC
eB 0.75 BSC
eC 1.50 BSC
L 0.20 0.40
L2 0.10 REF
GENERIC
MARKING DIAGRAM*
XXXXM
G
XXXX = Specific Device Code
M = Date Code
G = Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
17X
0.30
1.80
6X
0.13
3X
0.50
1
0.45
NOTE: CENTER PADS OPTIONAL
0.50
PITCH
1.50
PITCH
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
98AON84709E
UDFN18, 5.5X1.5, 0.5P/0.75P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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