ON Semiconductor MCR12DSM, MCR12DSN Technical data

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MCR12DSM, MCR12DSN

Preferred Device

Sensitive Gate
Silicon Contr olled Rectifiers

Reverse Blocking Thyristors

Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.

• Small Size

• Passivated Die for Reliability and Uniformity

• Low Level Triggering and Holding Characteristics

• Device Marking: Logo, Device T ype, e.g., R12DSM, Date Code

MAXIMUM RATINGS (T

Rating

Peak Repetitive Off–State V oltage

(TJ = –40 to 110°C, Sine Wave,
50 to 60 Hz, Gate Open)

On–State RMS Current

(180° Conduction Angles; TC = 75°C)

Average On–State Current

(180° Conduction Angles; TC = 75°C)

Peak Non-Repetitive Surge Current

(1/2 Cycle, Sine Wave 60 Hz,
TJ = 110°C)

Circuit Fusing Consideration

(t = 8.3 msec)

Forward Peak Gate Power

(Pulse Width ≤ 1.0 msec, TC = 75°C)

Forward Average Gate Power

(t = 8.3 msec, TC = 75°C)

Forward Peak Gate Current

(Pulse Width ≤ 1.0msec, TC = 75°C)
Operating Junction Temperature Range T
Storage Temperature Range T

(1) V

and V

DRM

apply for zero or negative gate voltage; however, positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.

RRM

= 25°C unless otherwise noted)

J

Symbol Value Unit

(1)

MCR12DSM
MCR12DSN

for all types can be applied on a continuous basis. Ratings

V

DRM,

V

RRM

600
800

I

T(RMS)

I

T(AV)

I

TSM

I2t 41 A2sec

P

GM

P

G(AV)

I

GM

J

stg

12 Amps

7.6 Amps

100 Amps

5.0 Watts

0.5 Watts

2.0 Amps

–40 to 110 °C
–40 to 150 °C

Volts

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SCRs

12 AMPERES RMS

600 thru 800 VOLTS

G

A

1

2

3

D–PAK

CASE 369A

STYLE 4

PIN ASSIGNMENT

1
2
3
4

ORDERING INFORMATION

Device Package Shipping

MCR12DSMT4 DPAK 369A 16mm Tape

MCR12DSNT4 DPAK 369A 16mm T ape

Preferred devices are recommended choices for future use
and best overall value.

K

4

Cathode

Anode

Gate

Anode

and Reel

(2.5K/Reel)

and Reel

(2.5K/Reel)

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 1

1 Publication Order Number:

MCR12DSM/D

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient

Maximum Lead Temperature for Soldering Purposes

(1)

MCR12DSM, MCR12DSN

(2)

R

q

JC

R

q

JA

R

q

JA

T

L

2.2
88
80

260 °C

°C/W

ELECTRICAL CHARACTERISTICS (T

Characteristics

= 25°C unless otherwise noted)

J

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Peak Repetitive Forward or Reverse Blocking Current

(VAK = Rated V

DRM

or V

; RGK = 1.0 KW)T

RRM

(3)

= 25°C

J

TJ = 110°C

I

DRM

I

RRM

,

—
—

—
—

10

500

m

A

ON CHARACTERISTICS

Peak Reverse Gate Blocking Voltage

(IGR = 10 mA)

Peak Reverse Gate Blocking Current

(VGR = 10 V)

Peak Forward On–State Voltage

(ITM = 20 A)

Gate Trigger Current (Continuous dc)

(VD = 12 V, RL = 100 W)T

Gate Trigger Voltage (Continuous dc)

(VD = 12 V, RL = 100 W)T

Holding Current

(VD = 12 V, Initiating Current = 200 mA, Gate Open) TJ = 25°C

Latching Current

(VD = 12 V, IG = 2.0 mA) TJ = 25°C

Turn–On Time

(Source Voltage = 12 V, RS = 6.0 KW, IT = 16 A(pk), RGK = 1.0 KW)
(VD = Rated V

, Rise Time = 20 ns, Pulse Width = 10 ms)

DRM

(4)

(5)

(5)

= 25°C

J

TJ = –40°C

= 25°C

J

TJ = –40°C
TJ = 110°C

TJ = –40°C

TJ = –40°C

V

GRM

I

GRM

V

I

V

TM

GT

GT

I

H

I

tgt

10 12.5 18

— — 1.2

— 1.3 1.9

5.0
—

0.45
—

0.2

0.5
—

L

0.5
—

— 2.0 5.0

12
—

0.65
—
—

1.0
—

1.0
—

200
300

1.0

1.5
—

6.0
10

6.0
10

Volts

m

A

Volts

m

A

Volts

mA

mA

m

s

DYNAMIC CHARACTERISTICS

Characteristics Symbol Min Typ Max Unit

Critical Rate of Rise of Off–State Voltage

(VD = 0.67 X Rated V
RGK = 1.0 KW, TJ = 110°C)

(1) Surface mounted on minimum recommended pad size.
(2) 1/8″ from case for 10 seconds.
(3) Ratings apply for negative gate voltage or RGK = 1.0 KW. Devices shall not have a positive gate voltage concurrently with a negative voltage

on the anode. Devices should not be tested with a constant current source for forward and reverse blocking capability such that the voltage

applied exceeds the rated blocking voltage.
(4) Pulse Test: Pulse Width ≤ 2.0 msec, Duty Cycle ≤ 2%.
(5) RGK current not included in measurement.

, Exponential Waveform,

DRM

dv/dt

2.0 10 —

V/ms

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2

MCR12DSM, MCR12DSN

110

16

Voltage Current Characteristic of SCR

+ Current

Anode +

Symbol Parameter

°

V

DRM

I

DRM

V

RRM

I

RRM

V

TM

I

H

105
100

95
90
85

Peak Repetitive Off State Forward Voltage
Peak Forward Blocking Current
Peak Repetitive Off State Reverse Voltage
Peak Reverse Blocking Current
Peak On State Voltage
Holding Current

I

at V

RRM

Reverse Avalanche Region

Anode –

dc

RRM

Reverse Blocking Region

(off state)

14
12
10

8.0

6.0

on state

a

a

= Conduction

Angle

a

V

TM

I

H

Forward Blocking Region

(off state)

= 30°

I

DRM

60°

at V

90°

+ Voltage

DRM

120°

180°

dc

80
75

70

, MAXIMUM ALLOWABLE CASE TEMPERATURE ( C)

C

T

a

a

= Conduction

Angle

1.0 2.0 3.0 1.0 2.0
I

, AVERAGE ON–STATE CURRENT (AMPS)

T(AV)

a

= 30°

4.0 5.0

60°

90°

6.0 7.0

180°

120°

8.00

4.0

2.0

, A VERAGE POWER DISSIPATION (WATTS)

(AV)

P

0

I

, AVERAGE ON–STATE CURRENT (AMPS)

T(AV)

4.0

3.0 8.00

5.0

Figure 1. Average Current Derating Figure 2. On–State Power Dissipation

6.0

7.0

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3

100

1.0

10

1.0

0.1

, INSTANTANEOUS ON–STATE CURRENT (AMPS)

T

I

MCR12DSM, MCR12DSN

TYPICAL @ TJ = 25°C

MAXIMUM @ TJ = 110°C

0.1

MAXIMUM @ TJ = 25°C

(NORMALIZED)

, TRANSIENT THERMAL RESISTANCE

(t)

r

1.0 3.0 10 100 1000 10 K

VT, INSTANTANEOUS ON–STATE VOLTAGE (VOLTS)

2.0

4.0

5.00

0.01

1.00.1
t, TIME (ms)

Figure 3. On–State Characteristics Figure 4. Transient Thermal Response

Z

= R

q

JC(t)

q

JC(t)

S

r(t)

1000

m

100

10

, GATE TRIGGER CURRENT ( A)I

GT

1.0
–25 20–40

–10

TJ, JUNCTION TEMPERATURE (°C)

GATE OPEN

35

50 11065 5.0 11035 50

Figure 5. T ypical Gate Trigger Current versus

Junction T emperature

10

RGK = 1.0 K

RGK = 1.0 K

80

W

1.0

W

, GATE TRIGGER VOLTAGE (VOLTS)

GT

V

0.1

95

–25 65–40

–10 9580

TJ, JUNCTION TEMPERATURE (°C)

205.0

Figure 6. T ypical Gate Trigger Voltage versus

Junction T emperature

10

RGK = 1.0 K

W

1.0

, HOLDING CURRENT (mA)

H

I

0.1
–25 5.0 20 50 95

–10 35 80

TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

65 110–40

Figure 7. T ypical Holding Current versus

Junction T emperature

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1.0

, LATCHING CURRENT (mA)

L

I

0.1
–25 5.0 20 50 95

–10 35 80

65 110–40

Figure 8. T ypical Latching Current versus

Junction T emperature

4

10

1000

, HOLDING CURRENT (mA)

H

I

8.0

6.0

4.0

2.0

IGT = 25 mA

IGT = 10 mA

MCR12DSM, MCR12DSN

TJ = 25°C

100

m

10

STATIC dv/dt (V/ s)

70°C

90°C

TJ = 110°C

0

1000 10 K100

RGK, GATE–CATHODE RESISTANCE (OHMS)

Figure 9. Holding Current versus

Gate–Cathode Resistance

1.0
100

RGK, GATE–CATHODE RESISTANCE (OHMS)

Figure 10. Exponential Static dv/dt versus

Gate–Cathode Resistance and Junction

1000

T emperature

1000

TJ = 110°C

400 V

100

m

10

STATIC dv/dt (V/ s)

1.0

VPK = 800 V

100

600 V

1000

RGK, GATE–CATHODE RESISTANCE (OHMS)

Figure 11. Exponential Static dv/dt versus

Gate–Cathode Resistance and Peak V oltage

1000

100

m

STATIC dv/dt (V/ s)

IGT = 25 mA

IGT = 10 mA

10

1.0
100

Figure 12. Exponential Static dv/dt versus

Gate–Cathode Resistance and Gate Trigger

VD = 800 V
TJ = 110°C

1000

RGK, GATE–CATHODE RESISTANCE (OHMS)

Current Sensitivity

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5

MCR12DSM, MCR12DSN

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection

0.165

4.191

0.190

4.826

interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.

0.118

0.100

2.54

3.0

0.063

1.6

0.243

6.172

inches

mm

DPAK

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6

MCR12DSM, MCR12DSN

P ACKAGE DIMENSIONS

D–P AK

CASE 369A–13

ISSUE Z

NOTES:

SEATING

–T–

PLANE

B

V

S

R

4

A

123

K

F

L

D

2 PL

G

0.13 (0.005) T

C

E

Z

U

J

H

M

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.033 0.040 0.84 1.01
F 0.037 0.047 0.94 1.19
G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.175 0.215 4.45 5.46
S 0.020 0.050 0.51 1.27
U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
Z 0.138 ––– 3.51 –––

STYLE 4:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

MILLIMETERSINCHES

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7

MCR12DSM, MCR12DSN

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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MCR12DSM/D