ON Semiconductor MC74LVXT4066 Technical data

MC74LVXT4066

Quad Analog Switch/
Multiplexer/Demultiplexer

High–Performance Silicon–Gate CMOS

The MC74LVXT4066 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
OFF–channel leakage current. This bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power–supply range (from VCC to GND).

The LVXT4066 is identical in pinout to the metal–gate CMOS
MC14066 and the high–speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
resistances (RON) are much more linear over input voltage than R
of metal–gate CMOS analog switches.

The ON/OFF control inputs are compatible with standard LSTTL
outputs. The input protection circuitry on this device allows
overvoltage tolerance on the ON/OFF control inputs, allowing the
device to be used as a logic–level translator from 3.0V CMOS logic to

5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic
while operating at the higher–voltage power supply.

The MC74LVXT4066 input structure provides protection when voltages
up to 7V are applied, regardless of the supply voltage. This allows the
MC74L VXT4066 to be used to interface 5V circuits to 3V circuits.

• Fast Switching and Propagation Speeds

• High ON/OFF Output Voltage Ratio

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Wide Power–Supply Voltage Range (V

• Analog Input Voltage Range (V

CC

– GND) = 2.0 to 6.0 Volts

CC

– GND) = 2.0 to 6.0 Volts

• Improved Linearity and Lower ON Resistance over Input Voltage

than the MC14016 or MC14066

• Low Noise

LOGIC DIAGRAM

12

X

A

A ON/OFF CONTROL

B ON/OFF CONTROL

C ON/OFF CONTROL

D ON/OFF CONTROL
ANALOG INPUTS/OUTPUTS = XA, XB, XC, X

PIN 14 = V
PIN 7 = GND

CC

13
43

X

B

5
89

X

C

6
11 10

X

D

12

D

Y

A

Y

B

ANALOG
OUTPUTS/INPUTS

Y

C

Y

D

ON

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14–LEAD SOIC

D SUFFIX

CASE 751A

14–LEAD TSSOP

DT SUFFIX

CASE 948G

PIN CONNECTION AND

MARKING DIAGRAM (Top View)

X
Y
Y
X

B ON/OFF

CONTROL

C ON/OFF

CONTROL

GND

For detailed package marking information, see the Marking
Diagram section on page 10 of this data sheet.

1

A

2

A

3

B

4

B

6
7

V

14
13
12
11
105

9
8

CC
A ON/OFF
CONTROL

D ON/OFF
CONTROL

X

D
Y

D
Y

C
X

C

FUNCTION TABLE

On/Off Control

Input

L

H

State of

Analog Switch

Off
On

ORDERING INFORMATION

Device Package Shipping

MC74L VXT4066D SOIC 55 Units/Rail
MC74L VXT4066DR2 SOIC
MC74L VXT4066DT TSSOP 96 Units/Rail
MC74L VXT4066DTR2 TSSOP

2500 Units/Reel

2500 Units/Reel

 Semiconductor Components Industries, LLC, 1999

March, 2000 – Rev . 1

1 Publication Order Number:

MC74LVXT4066/D

MC74LVXT4066

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MAXIMUM RATINGS*

Symbol

V

T

Positive DC Supply Voltage (Referenced to GND)

CC

V

Analog Input Voltage (Referenced to GND)

IS

V

Digital Input Voltage (Referenced to GND)

in
I

DC Current Into or Out of Any Pin

P

Power Dissipation in Still Air, SOIC Package†

D

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

V

V

VIO*

T

tr, t

ÎÎ

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.

Positive DC Supply Voltage (Referenced to GND)

CC

Analog Input Voltage (Referenced to GND)

IS

Digital Input Voltage (Referenced to GND)

in

Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types

A

Input Rise and Fall Time, ON/OFF Control

f

Inputs (Figure 10) VCC = 3.3 V ± 0.3 V

ООООООООООООО

Parameter

Parameter

TSSOP Package†

VCC = 5.0 V ± 0.5 V

Value

– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5

–20
500

450

– 65 to + 150

260

Min

Max

2.0

5.5

GND

V

CC

GND

V

CC

—

1.2

– 55

+ 85

0

100

Î

0

20

Unit

mA

mW

_

_

Unit

_

ns/V

Î

This device contains protection

V
V
V

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

should be constrained to the

out

C
C

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).

range GND v (Vin or V

) v VCC.

out

Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.

V
V
V
V

C

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

V

ÎÎ

Symbol

V

ÎÎ

V

ÎÎ

ÎÎ

I

ОООООООО

Minimum High–Level Voltage

IH

ON/OFF Control Inputs

ОООООООО

(Note 1)
Maximum Low–Level Voltage

IL

ON/OFF Control Inputs

ОООООООО

(Note 1)

I

CC

Maximum Input Leakage Current

in

ОООООООО

ON/OFF Control Inputs
Maximum Quiescent Supply

Current (per Package)

Parameter

ООООО

Test Conditions

Ron = Per Spec

ООООО

Ron = Per Spec

ООООО

Vin = VCC or GND

ООООО

Vin = VCC or GND
VIO = 0 V

1. Specifications are for design target only. Not final specification limits.

CC

ÎÎÎ

V

3.0

4.5

ÎÎÎ

5.5

3.0

4.5

ÎÎÎ

5.5

5.5

ÎÎÎ

5.5

Guaranteed Limit

– 55 to

ÎÎ

25_C

1.2

2.0

ÎÎ

2.0

0.53

0.8

ÎÎ

0.8

± 0.1

ÎÎ

4.0

v

Î

85_C

1.2

2.0

Î

2.0

0.53

0.8

Î

0.8

± 1.0

Î

40

ÎÎ

v

125_C

1.2

2.0

ÎÎ

2.0

0.53

0.8

ÎÎ

0.8

± 1.0

ÎÎ

160

Î

Unit

Î

Î

µA

Î

µA

V

V

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2

MC74LVXT4066

ÎÎÎ

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

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Î

Î

Î

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Î

Î

Î

Î

Î

Î

ÎÎÎ

Î

Î

Î

Î

Î

Î

Î

Î

ÎÎÎ

Î

Î

Î

ÎÎÎ

Î

Î

Î

Î

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

Guaranteed Limit

V

Symbol

R

on

ÎÎ

ÎÎ

ÎÎ

ÎÎ

∆R

on

ÎÎ

I

off

ÎÎ

ÎÎ

I

on

ÎÎ

Maximum “ON” Resistance

ОООООООО

ОООООООО

ОООООООО

ОООООООО

Maximum Difference in “ON”
Resistance Between Any Two

ОООООООО

Channels in the Same Package
Maximum Off–Channel Leakage

ОООООООО

Current, Any One Channel

ОООООООО

Maximum On–Channel Leakage
Current, Any One Channel

ОООООООО

Parameter

Test Conditions

Vin = V

IH

ОООООО

VIS = VCC to GND
IS v 2.0 mA (Figures 1, 2)

ОООООО

Vin = V

IH

VIS = VCC or GND (Endpoints)

ОООООО

IS v 2.0 mA (Figures 1, 2)

ОООООО

Vin = V

IH

VIS = 1/2 (VCC – GND)

ОООООО

IS v 2.0 mA
Vin = V

IL

ОООООО

VIO = VCC or GND
Switch Off (Figure 3)

ОООООО

Vin = V

IH

VIS = VCC or GND
(Figure 4)

ОООООО

2.0†

ÎÎ

3.0

4.5

ÎÎ

5.5

2.0

3.0

ÎÎ

4.5

ÎÎ

5.5

3.0

4.5

ÎÎ

5.5

5.5

ÎÎ

ÎÎ

5.5

ÎÎ

†At supply voltage (VCC) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage

operation, it is recommended that these devices only be used to control digital signals.

CC
V

– 55 to

25_C

—

ÎÎ

40
25

ÎÎ

20

—

30

ÎÎ

25

ÎÎ

20
15

10

ÎÎ

10

0.1

ÎÎ

ÎÎ

0.1

ÎÎ

v

85_C

—

Î

45
28

Î

25
—

35

Î

28

Î

25
20

12

Î

12

0.5

Î

Î

0.5

Î

v

125_C

—

ÎÎ

50
35

ÎÎ

30
—

40

ÎÎ

35

ÎÎ

30
25

15

ÎÎ

15

1.0

ÎÎ

ÎÎ

1.0

ÎÎ

Unit

Ω

Î

Î

Î

Î

Ω

Î

µA

Î

Î

µA

Î

AC ELECTRICAL CHARACTERISTICS (C

ÎÎÎ

Symbol

t

,

PLH

t

PHL

ÎÎÎ

ÎÎÎ

t

,

PLZ

t

PHZ

ÎÎÎ

ÎÎÎ

t

,

PZL

t

PZH

ÎÎÎ

ÎÎÎ

C

ОООООООООООООО

Maximum Propagation Delay , Analog Input to Analog Output

(Figures 8 and 9)

ОООООООООООООО

ОООООООООООООО

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

ОООООООООООООО

ОООООООООООООО

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 1 1)

ОООООООООООООО

ОООООООООООООО

Maximum Capacitance ON/OFF Control Input

= 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

L

Parameter

Control Input = GND

Analog I/O

ÎÎÎÎОООООООООООООО

C

PD

Power Dissipation Capacitance (Per Switch) (Figure 13)*

Feedthrough

*Used to determine the no–load dynamic power consumption: PD = CPD V

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

2

f + ICC VCC.

CC

Guaranteed Limit

V

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5
—

—
—

CC
V

– 55 to

ÎÎ

25_C

4.0

3.0

ÎÎ

1.0

ÎÎ

1.0
30

20

ÎÎ

15
15

ÎÎ

20
12

ÎÎ

8.0

8.0

ÎÎ

10

35

1.0

ÎÎ

v

Î

85_C

6.0

5.0

Î

2.0

Î

2.0
35

25

Î

18
18

Î

25
14

Î

10
10

Î

10

35

1.0

Î

ÎÎ

v

125_C

8.0

6.0

ÎÎ

2.0

ÎÎ

2.0
40

30

ÎÎ

22
20

ÎÎ

30
15

ÎÎ

12
12

ÎÎ

10

35

1.0

ÎÎ

Î

Unit

Î

Î

Î

Î

Î

Î

pF

Î

ns

ns

ns

Typical @ 25°C, VCC = 5.0 V

15

pF

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3

MC74LVXT4066

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

Î

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

Symbol

ÎÎ

BW

ОООООООО

Maximum On–Channel Bandwidth
or Minimum Frequency Response

ÎÎ

—

ÎÎ

ÎÎ

—

ÎÎ

ÎÎ

—

ÎÎ

ÎÎ

THD

ÎÎ

ÎÎ

(Figure 5)

ОООООООО

Off–Channel Feedthrough Isolation

ОООООООО

(Figure 6)

ОООООООО

Feedthrough Noise, Control to

ОООООООО

Switch

(Figure 7)

ОООООООО

Crosstalk Between Any Two

ОООООООО

Switches

(Figure 12)

ОООООООО

Total Harmonic Distortion

ОООООООО

(Figure 14)

ОООООООО

*Guaranteed limits not tested. Determined by design and verified by qualification.

Parameter

ОООООООООООО

Test Conditions

fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
Increase fin Frequency Until dB Meter Reads – 3 dB

ОООООООООООО

OS

RL = 50 Ω, CL = 10 pF

fin  Sine Wave

ОООООООООООО

Adjust fin Voltage to Obtain 0 dBm at V

ОООООООООООО

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

IS

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

Vin v 1 MHz Square Wave (tr = tf = 3 ns)

ОООООООООООО

Adjust RL at Setup so that IS = 0 A

ОООООООООООО

RL = 600 Ω, CL = 50 pF

RL = 10 kΩ, CL = 10 pF

fin  Sine Wave

ОООООООООООО

Adjust fin Voltage to Obtain 0 dBm at V

ОООООООООООО

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

IS

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

fin = 1 kHz, RL = 10 kΩ, CL = 50 pF

ОООООООООООО

THD = THD

ОООООООООООО

Measured

– THD

Source

VIS = 4.0 VPP sine wave
VIS = 5.0 VPP sine wave

V

CC

Î

4.5

5.5

Î

4.5

Î

5.5

Î

4.5

5.5

4.5

Î

5.5

Î

4.5

5.5

4.5

Î

5.5

Î

4.5

5.5

Î

4.5

Î

5.5

V

25_C

ÎÎ

150

Unit

Î

MHz

160

Limit*

ÎÎ

– 50

ÎÎ

– 50

ÎÎ

Î

dB

Î

Î

– 37
– 37

100

ÎÎ

200

ÎÎ

mV

Î

Î

PP

50

100

– 70

ÎÎ

– 70

ÎÎ

dB

Î

Î

– 80
– 80

ÎÎ

0.10

ÎÎ

Î

Î

%

0.06

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4

MC74LVXT4066

400

250

350
300
250
200

Ron (Ohms)

150
100

50

0

0.5 1

–55°C

25°C

85°C

125°C

1.5 2 2.50

Vin (Volts)

200

150

Ron (Ohms)

100

50

0

Is = 9mA

0.5 1

Is = 1mA

Is = 5mA

Is = 15mA

1.5 2 2.50

Vin (Volts)

Figure 1a. T ypical On Resistance, VCC = 2.0 V, T = 25°C Figure 1b. T ypical On Resistance, VCC = 2.0 V

35

30

25

20

15

Ron (Ohms)

10

5

125°C

85°C

25°C

–55°C

25

20

15

Ron (Ohms)

10

5

125°C
85°C

–55°C

25°C

0

1

20

Vin (Volts)

Figure 1c. T ypical On Resistance, VCC = 3.0 V

18
16
14
12
10

8

Ron (Ohms)

6
4
2
0

12

Vin (Volts)

3450

Figure 1e. T ypical On Resistance, VCC = 5.5 V

3

4

0

12

Vin (Volts)

3450

Figure 1d. T ypical On Resistance, VCC = 4.5 V

PLOTTER

125°C

85°C
25°C

–55°C

6

PROGRAMMABLE

POWER
SUPPLY

+–

ANALOG IN COMMON OUT

MINI COMPUTER

DEVICE

UNDER TEST

GND

DC ANALYZER

V

CC

Figure 2. On Resistance T est Set–Up

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5

MC74LVXT4066

V

CC

V

CC

OFF

SELECTED

CONTROL

INPUT

14

V

IL

GND

V

CC

A

7

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up

V

V

14

f

in

0.1µF

7

ON

SELECTED

CONTROL

INPUT

CC

OS

CL*

V

CC

METER

dB

V

V

GND

CC

A

7

ON

SELECTED

CONTROL

INPUT

CC

14

V

IH

Figure 4. Maximum On Channel Leakage Current,

T est Set–Up

V

V

IS

f

in

0.1µF

R

L

SELECTED
CONTROL
INPUT

7

V

14

OFF

CC

OS

CL*

N/C

dB

METER

*Includes all probe and jig capacitance.

Figure 5. Maximum On–Channel Bandwidth

T est Set–Up

INPUT

V

CC

14

V

CC/2

R

L

OFF/ON

SELECTED

CONTROL

Vin ≤ 1 MHz
tr = tf = 3 ns

V

IH

V

IL

*Includes all probe and jig capacitance.

CONTROL

7

Figure 7. Feedthrough Noise, ON/OFF Control to

Analog Out, Test Set–Up

*Includes all probe and jig capacitance.

Figure 6. Off–Channel Feedthrough Isolation,

T est Set–Up

V

CC/2

R

L

V

CL*

OS

ANALOG IN

t

PLH

ANALOG OUT

50%

50%

t

PHL

V

CC

GND

I

S

Figure 8. Propagation Delays, Analog In to

Analog Out

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6

MC74LVXT4066

14

ON

SELECTED

CONTROL

7

*Includes all probe and jig capacitance.

ANALOG OUTANALOG IN

INPUT

Figure 9. Propagation Delay T est Set–Up

POSITION WHEN TESTING t
1
2

V

CC

1
2

V

IH

V

IL

*Includes all probe and jig capacitance.

POSITION WHEN TESTING t

1
2

ON/OFF

SELECTED
CONTROL
INPUT

7

V

CC

TEST

POINT

CL*

V

IH

CONTROL

ANALOG

OUT

50%

10%

90%

t

r

50%

50%

t

PZL

t

PZH

t

PLZ

t

PHZ

t

f

V

CC

GND

HIGH
IMPEDANCE

10%

90%

V

OL

V

OH

HIGH
IMPEDANCE

Figure 10. Propagation Delay , ON/OFF Control

to Analog Out

AND t

PHZ

PLZ

V

CC

14

AND t

1 kΩ

CL*

PZH

PZL

TEST

POINT

f

in

0.1 µF

VIH OR V

*Includes all probe and jig capacitance.

V

IS

R

L

IL

R

L

V

CC/2

ON

OFF

SELECTED
CONTROL
INPUT

7

V

CC

14

R

CL*

L

V

CC/2

V

CC/2

V

OS

R

CL*

L

Figure 11. Propagation Delay Test Set–Up

14

N/C

V

IH

V

IL

ON/OFF CONTROL

OFF/ON

7

SELECTED

CONTROL

INPUT

Figure 13. Power Dissipation Capacitance

Test Set–Up

Figure 12. Crosstalk Between Any Two Switches,

T est Set–Up

V

CC

A

N/C

f

in

*Includes all probe and jig capacitance.

0.1 µF

V

IS

7

ON

SELECTED

CONTROL

INPUT

V

CC

V

CC/2

V

V

OS

TO

DISTORTION

CL*

R

L

IH

METER

Figure 14. Total Harmonic Distortion, T est Set–Up

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7

dBm

–10
–20
–30
–40
–50
–60
–70
–80
–90

MC74LVXT4066

0

FUNDAMENTAL FREQUENCY

DEVICE
SOURCE

1.0 2.0

Figure 15. Plot, Harmonic Distortion

APPLICATION INFORMATION

The ON/OFF Control pins should be at VIH or VIL logic
levels, VIH being recognized as logic high and VIL being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
advisable to tie unused analog inputs and outputs to VCC or
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked–up by the unused
I/O pins.

The maximum analog voltage swings are determined by
the supply voltages VCC and GND. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below GND. In the example
below, the difference between VCC and GND is six volts.

VCC = 6.0 V

ON

14

ANALOG O/I

+ 6.0 V

0 V

ANALOG I/O

3.0

FREQUENCY (kHz)

Therefore, using the configuration in Figure 16, a maximum
analog signal of six volts peak–to–peak can be controlled.

When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn–on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
Mosorbs (Mosorb is an acronym for high current surge
protectors). Mosorbs are fast turn–on devices ideally suited
for precise DC protection with no inherent wear out
mechanism.

+ 6.0 V

0 V

V

CC

D

x

ON

D

x

V

CC

16

D

x

D

x

SELECTED

V

IH

CONTROL
INPUT

7

OTHER CONTROL

INPUTS

(VIH OR VIL)

V

IH

SELECTED
CONTROL
INPUT

7

OTHER CONTROL

INPUTS

(VIH OR VIL)

Figure 16. 6.0 V Application Figure 17. Transient Suppressor Application

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8

MC74LVXT4066

+3

+5

G

S

V

+3V

GND

1.8 – 2.5V

CIRCUITRY

ANALOG
SIGNALS

R* = 2 TO 10 kΩ

14
15

5
6

14

LVXT4066

CONTROL

INPUTS

7

ANALOG

SIGNALS

+3V

GND

V

LSTTL/
NMOS/

ABT/

ALS

ANALOG
SIGNALS

14
15

5
6

LVXT4066

CONTROL

INPUTS

a. Low Voltage Logic Level Shifting Control b. Using LVXT4066

Figure 18. Low Voltage CMOS Interface

CHANNEL 4

CHANNEL 3

CHANNEL 2

1 OF 4

SWITCHES

1 OF 4

SWITCHES

COMMON I/O

1 OF 4

SWITCHES

14

7

ANALO
SIGNAL

CHANNEL 1

0.01 µF

–
+

EQUIVALENT

LF356 OR

1 OF 4

SWITCHES

1234

CONTROL INPUTS

INPUT

1 OF 4

SWITCHES

Figure 19. 4–Input Multiplexer Figure 20. Sample/Hold Amplifier

OUTPUT

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9

MC74LVXT4066

MARKING DIAGRAMS

(Top View)

SEATING
PLANE

1314 12 11 10 9 8

LVXT4066

1314 12 11 10 9 8

LVXT

4066

AWLYWW*

21 34567

14–LEAD SOIC

D SUFFIX

CASE 751A

ALYW*

21 34567

14–LEAD TSSOP

DT SUFFIX

CASE 948G

*See Applications Note #AND8004/D for date code and traceability information.

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

–A–

814

P 7 PL

–B–

M M

1

G

D 14 PL

0.25 (0.010) T B A

7

X 45°

C

R

K

M

S S

B0.25 (0.010)

M

J

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

F

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A
B
C
D
F

G

J
K

M

P
R

8.75

8.55

4.00

3.80

1.75

1.35

0.49

0.35

1.25

0.40

1.27 BSC 0.050 BSC

0.25

0.19

0.25

0.10
7°

0°

6.20

5.80

0.50

0.25

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009
7°

0°

0.244

0.019

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10

MC74LVXT4066

ÉÉ

P ACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

–T–

0.10 (0.004)

SEATING
PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1
IDENT.

1

S

U0.15 (0.006) T

A

–V–

B

–U–

N

F

7

DETAIL E

K

K1

J

J1

SECTION N–N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008

–W–

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

INCHESMILLIMETERS

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11

MC74LVXT4066

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC74L VXT4066/D

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