MC74HC74A
Dual D Flip-Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q
outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
PIN 14 = VCC
PIN 7 = GND
Q1
Q1
Q2
Q2
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SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
RESET 1
DATA 1
CLOCK 1
SET 1
Q1
Q1
GND
1
2
3
4
6
7
14
13
12
11
105
9
8
V
CC
RESET 2
DATA 2
CLOCK 2
SET 2
Q2
Q2
MARKING DIAGRAMS
14
HC74AG
AWLYWW
1
SOIC−14 NB
14
HC
74A
ALYWG
G
1
TSSOP−14
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
1 Publication Order Number:
MC74HC74A/D
MC74HC74A
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_ C
DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V
CC
V
DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
in
DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V
out
I
DC Input Current, per Pin ±20 mA
in
I
DC Output Current, per Pin ±25 mA
out
I
DC Supply Current, VCC and GND Pins ±50 mA
CC
P
Power Dissipation in Still Air, SOIC Package†
D
TSSOP Package†
T
Storage Temperature –65 to +150
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
(SOIC or TSSOP Package)
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
500
450
260
300
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, V
should be constrained to the
V
out
range GND v (V
in
or V
) v VCC.
out
in
and
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
Unused outputs must be left open.
).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
Vin, V
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
CC
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
out
T
Operating Temperature, All Package Types –55 +125
A
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figures 1, 2, 3) V
V
V
= 3.0 V
CC
= 4.5 V
CC
= 6.0 V
CC
0
0
0
0
CC
1000
600
500
400
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HC74A
l
l
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
V
IH
V
IL
V
OH
V
OL
I
in
I
CC
Minimum High−Level Input
Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage
Maximum Low−Level Output
Voltage
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0
Maximum Quiescent Supply
Current (per Package)
Parameter Test Conditions
V
= 0.1 V or VCC – 0.1 V
out
|I
| v 20 mA
out
V
= 0.1 V or VCC – 0.1 V
out
|I
| v 20 mA
out
Vin = VIH or V
|I
| v 20 mA
out
Vin = VIH or VIL|I
Vin = VIH or V
|I
| v 20 mA
out
Vin = VIH or VIL|I
IL
IL
| v 2.4 mA
out
| v 4.0 mA
|I
out
|I
| v 5.2 mA
out
| v 2.4 mA
out
| v 4.0 mA
|I
out
|I
| v 5.2 mA
out
Vin = VCC or GND
I
= 0 mA
out
Guaranteed Limit
CC
V
–55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
v 85_C v 125_C
1.5
2.1
3.15
3.15
4.2
0.5
0.9
1.35
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0 2.0 20 80
1.5
2.1
4.2
0.5
0.9
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
Unit
V
V
V
V
mA
mA
AC ELECTRICAL CHARACTERISTICS (C
Symbo
f
max
Maximum Clock Frequency (50% Duty Cycle)
Parameter
= 50 pF, Input tr = t
L
= 6.0 ns)
f
(Figures 1 and 4)
t
,
Maximum Propagation Delay, Clock to Q or Q
PLH
t
t
PLH
t
t
TLH
t
C
PHL
PHL
THL
C
PD
in
(Figures 1 and 4)
,
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance — 10 10 10 pF
Power Dissipation Capacitance (Per Flip−Flop)*
*Used to determine the no−load dynamic power consumption: PD = CPD V
2
f + ICC VCC.
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
CC
V
Guaranteed Limit
– 55 to
25_C
6.0
15
30
35
100
75
20
17
105
80
21
18
75
30
15
13
v 85_C v 125_C
4.8
10
24
28
125
90
25
21
130
95
26
22
95
40
19
16
Typical @ 25°C, VCC = 5.0 V
32
4.0
8.0
20
24
150
120
30
26
160
130
32
27
110
55
22
19
Unit
MHz
ns
ns
ns
pF
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3
MC74HC74A
l
TIMING REQUIREMENTS (Input t
Symbo
t
Minimum Setup Time, Data to Clock
t
tr, t
t
rec
t
t
su
h
w
w
(Figure 3)
Minimum Hold Time, Clock to Data
(Figure 3)
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
Minimum Pulse Width, Clock
(Figure 1)
Minimum Pulse Width, Set or Reset
(Figure 2)
Maximum Input Rise and Fall Times
f
(Figures 1, 2, 3)
= tf = 6.0 ns)
r
Parameter
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
CC
V
Guaranteed Limit
–55 to
25_C
80
35
16
14
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
60
25
12
10
60
25
12
10
1000
800
500
400
v 85_C v 125_C
100
45
20
17
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
75
30
15
13
75
30
15
13
1000
800
500
400
120
55
24
20
3.0
3.0
3.0
3.0
8.0
8.0
8.0
8.0
90
40
18
15
90
40
18
15
1000
800
500
400
Unit
ns
ns
ns
ns
ns
ns
ORDERING INFORMATION
Device Package Shipping
MC74HC74ADG SOIC−14 NB
55 Units / Rail
(Pb−Free)
NLV74HC74ADG* SOIC−14 NB
55 Units / Rail
(Pb−Free)
MC74HC74ADR2G SOIC−14 NB
2500 / Tape & Reel
(Pb−Free)
NLV74HC74ADR2G* SOIC−14 NB
2500 / Tape & Reel
(Pb−Free)
MC74HC74ADTR2G TSSOP−14
2500 / Tape & Reel
(Pb−Free)
NLV74HC74ADTR2G* TSSOP−14
2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
†
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4
CLOCK
Q or Q
10%
90%
50%
50%
10%
90%
MC74HC74A
SWITCHING WAVEFORMS
t
50%
50%
50%
w
V
CC
GND
t
PHL
t
PLH
t
rec
V
CC
50%
GND
t
f
t
w
t
PLH
t
r
1/f
max
t
PHL
V
CC
GND
SET OR
RESET
Q
OR Q
Q OR Q
t
TLH
t
THL
CLOCK
CLOCK
SET
DATA
DATA
4, 10
2, 12
50%
t
su
Figure 1.
VALID
t
h
50%
Figure 3.
V
CC
GND
V
CC
GND
Figure 2.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 4.
5, 9
Q
RESET
1, 13
3, 11
CLOCK
Figure 5. EXPANDED LOGIC DIAGRAM
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5
6, 8
Q
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
14
1
SCALE 1:1
SOIC−14 NB
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
14
H
M
0.25 B
0.10
14X
0.58
D
M
13X
e
SOLDERING FOOTPRINT*
6.50
1
A
B
8
E
71
b
S
M
0.25 B
A
C
A
A1
SEATING
C
PLANE
14X
1.18
S
1.27
PITCH
DETAIL A
h
X 45
_
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3
L
DETAIL A
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
b 0.35 0.49 0.014 0.019
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
L 0.40 1.25 0.016 0.049
M 0 7 0 7
__ __
INCHESMILLIMETERS
GENERIC
MARKING DIAGRAM*
14
XXXXXXXXXG
AWLYWW
1
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
14
1
SCALE 2:1
0.10 (0.004)
SEATING
−T−
PLANE
S
U0.15 (0.006) T
2X L/2
L
PIN 1
IDENT.
S
U0.15 (0.006) T
C
D
SOLDERING FOOTPRINT
1
14X REFK
0.10 (0.004) V
14
1
M
8
7
A
−V−
G
7.06
TSSOP−14 WB
U
T
B
N
−U−
J
H
CASE 948G
ISSUE C
S
S
N
F
DETAIL E
J1
SECTION N−N
DETAIL E
0.25 (0.010)
M
K
K1
DATE 17 FEB 2016
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
INCHESMILLIMETERS
−W−
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
GENERIC
MARKING DIAGRAM*
14
XXXX
XXXX
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
0.65
PITCH
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
14X
0.36
DOCUMENT NUMBER:
DESCRIPTION:
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
14X
1.26
98ASH70246A
TSSOP−14 WB
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
PAGE 1 OF 1
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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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