ON Semiconductor MC74HC74A User Manual

MC74HC74A

Dual D Flip-Flop with Set
and Reset

High−Performance Silicon−Gate CMOS

The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.

This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q

outputs are available from each flip−flop. The Set

and Reset inputs are asynchronous.

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 128 FETs or 32 Equivalent Gates

• NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

LOGIC DIAGRAM

RESET 1

DATA 1

CLOCK 1

SET 1

RESET 2

DATA 2

CLOCK 2

SET 2

1

2

3

4

13

12

11

10

5

6

9

8

PIN 14 = VCC
PIN 7 = GND

Q1

Q1

Q2

Q2

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SOIC−14 NB

D SUFFIX

CASE 751A

TSSOP−14
DT SUFFIX

CASE 948G

PIN ASSIGNMENT

RESET 1

DATA 1

CLOCK 1

SET 1

Q1
Q1

GND

1
2
3
4

6
7

14
13
12
11
105

9
8

V

CC

RESET 2
DATA 2

CLOCK 2
SET 2

Q2
Q2

MARKING DIAGRAMS

14

HC74AG

AWLYWW

1

SOIC−14 NB

14

HC

74A

ALYWG

G

1

TSSOP−14

A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package

(Note: Microdot may be in either location)

© Semiconductor Components Industries, LLC, 2014

August, 2014 − Rev. 14

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

1 Publication Order Number:

MC74HC74A/D

MC74HC74A

FUNCTION TABLE

Inputs Outputs

Set Reset Clock Data Q Q

LH XX HL

HL XX LH

L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change

*Both outputs will remain high as long as Set

and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_ C

DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V

CC

V

DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V

in

DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V

out

I

DC Input Current, per Pin ±20 mA

in

I

DC Output Current, per Pin ±25 mA

out

I

DC Supply Current, VCC and GND Pins ±50 mA

CC

P

Power Dissipation in Still Air, SOIC Package†

D

TSSOP Package†

T

Storage Temperature –65 to +150

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

(SOIC or TSSOP Package)

TSSOP Package: −6.1 mW/_C from 65_ to 125_C

500
450

260
300

mW

_C
_C

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, V

should be constrained to the

V

out

range GND v (V

in

or V

) v VCC.

out

in

and

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

Vin, V

DC Supply Voltage (Referenced to GND) 2.0 6.0 V

CC

DC Input Voltage, Output Voltage (Referenced to GND) 0 V

out

T

Operating Temperature, All Package Types –55 +125

A

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figures 1, 2, 3) V

V
V

= 3.0 V

CC

= 4.5 V

CC

= 6.0 V

CC

0
0
0
0

CC

1000

600
500
400

V

_C

ns

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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MC74HC74A

l

l

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbo

V

IH

V

IL

V

OH

V

OL

I

in

I

CC

Minimum High−Level Input
Voltage

Maximum Low−Level Input
Voltage

Minimum High−Level Output
Voltage

Maximum Low−Level Output
Voltage

Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0
Maximum Quiescent Supply

Current (per Package)

Parameter Test Conditions

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 mA

out

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 mA

out

Vin = VIH or V
|I

| v 20 mA

out

Vin = VIH or VIL|I

Vin = VIH or V
|I

| v 20 mA

out

Vin = VIH or VIL|I

IL

IL

| v 2.4 mA

out

| v 4.0 mA

|I

out

|I

| v 5.2 mA

out

| v 2.4 mA

out

| v 4.0 mA

|I

out

|I

| v 5.2 mA

out

Vin = VCC or GND
I

= 0 mA

out

Guaranteed Limit

CC

V

–55 to

25_C

1.5

2.1

3.15

4.2

0.5

0.9

1.35

1.8

1.9

4.4

5.9

2.48

3.98

5.48

0.1

0.1

0.1

0.26

0.26

0.26

v 85_C v 125_C

1.5

2.1

3.15

3.15

4.2

0.5

0.9

1.35

1.35

1.8

1.9

4.4

5.9

2.34

3.84

5.34

0.1

0.1

0.1

0.33

0.33

0.33

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

2.0

4.5

6.0

3.0

4.5

6.0

6.0 2.0 20 80

1.5

2.1

4.2

0.5

0.9

1.8

1.9

4.4

5.9

2.2

3.7

5.2

0.1

0.1

0.1

0.4

0.4

0.4

Unit

V

V

V

V

mA
mA

AC ELECTRICAL CHARACTERISTICS (C

Symbo

f

max

Maximum Clock Frequency (50% Duty Cycle)

Parameter

= 50 pF, Input tr = t

L

= 6.0 ns)

f

(Figures 1 and 4)

t

,

Maximum Propagation Delay, Clock to Q or Q

PLH

t

t

PLH

t

t

TLH

t

C

PHL

PHL

THL

C

PD

in

(Figures 1 and 4)

,

Maximum Propagation Delay, Set or Reset to Q or Q

(Figures 2 and 4)

,

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

Maximum Input Capacitance — 10 10 10 pF

Power Dissipation Capacitance (Per Flip−Flop)*

*Used to determine the no−load dynamic power consumption: PD = CPD V

2

f + ICC VCC.

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

CC

V

Guaranteed Limit

– 55 to

25_C

6.0
15
30
35

100

75
20
17

105

80
21
18

75
30
15
13

v 85_C v 125_C

4.8
10
24
28

125

90
25
21

130

95
26
22

95
40
19
16

Typical @ 25°C, VCC = 5.0 V

32

4.0

8.0
20
24

150
120

30
26

160
130

32
27

110

55
22
19

Unit

MHz

ns

ns

ns

pF

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