ON Semiconductor MC74HC573A Technical data

MC74HC573A

Octal 3−State Noninverting
Transparent Latch

High−Performance Silicon−Gate CMOS

The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.

Features

• Pb−Free Packages are Available*

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 A

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 218 FETs or 54.5 Equivalent Gates

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MARKING

DIAGRAMS

20

PDIP−20

N SUFFIX

20

1

20

1

20

1

CASE 738

SOIC WIDE−20

DW SUFFIX
CASE 751D

TSSOP−20
DT SUFFIX

CASE 948E

MC74HC573AN

AWLYYWW

1

20

HC573A

AWLYYWW

1

20

HC

573A

ALYW

1

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2004

December, 2004 − Rev. 10

1 Publication Order Number:

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.

MC74HC573A/D

MC74HC573A

Î

Î

Î

Î

Î

Î

D0

D1

D2

DATA

INPUTS

D3

D4

D5

D6

D7

LATCH ENABLE

OUTPUT ENABLE

Figure 1. LOGIC DIAGRAM Figure 2. PIN ASSIGNMENT

Output Latch
Enable Enable D Q

X = Don’t Care
Z = High Impedance

219

3

4

5

6

7

8

9

Q0

18

Q1

17

Q2

16

15

14

13

12

Q3

Q4

Q5

Q6

Q7

NONINVERTING

OUTPUTS

11

1

PIN 20 = V
PIN 10 = GND

CC

FUNCTION TABLE

Inputs Output

LHHH
LHLL
L L X No Change

HXXZ

OUTPUT

ENABLE

GND

D0

D1

D2

D3 5

D4

D5

D6

D7

1

2

3

4

6

7

8

9

10

20

V

CC

19

Q0

18

Q1

17

Q2

16

Q3

15

Q4

14

Q5

13

Q6

12

Q7

LATCH

11

ENABLE

Design Criteria

Internal Gate Count*

ОООООООО

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

ОООООООО

*Equivalent to a two−input NAND gate.

Value

54.5

ÎÎ

1.5

5.0

0.0075

ÎÎ

Units

ea.

Î

ns

W

pJ

Î

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2

MC74HC573A

Î

Î

Î

Î

Î

Î

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Î

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ÎÎ

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MAXIMUM RATINGS

Symbol

V

V

ÎÎ

ÎÎ

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

I

DC Output Current, per Pin

out

I

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

T

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are

ООООООООООООООООООООО

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

†Derating — Plastic DIP: –10 mW/C from 65 to 125C

SOIC Package: –7 mW/C from 65 to 125C
TSSOP Package: −6.1 mW/°C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, TSSOP or SOIC Package)

Value

– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5

± 20
± 35
± 75

750
500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

mA
mA
mA

mW

Î

C
C

Î

This device contains protection

V
V
V

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir­cuit. For proper operation, V
V

should be constrained to the

out

range GND  (V

in

or V

)  VCC.

out

in

and

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V

CC

Unused outputs must be left open.

).

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V

f

(Figure 1) V

ООООООООООООО

Parameter

V

= 4.5 V

CC

= 6.0 V

CC

Min

2.0
0

– 55

0
0

Î

0

Max

6.0

V

CC

+ 125

1000

500
400

Unit

V
V

C

ns

Î

ORDERING INFORMATION

Device Package Shipping

MC74HC573AN PDIP−20 1440 Units / Box
MC74HC573ANG PDIP−20

1440 Units / Box

(Pb−Free)
MC74HC573ADW SOIC−WIDE 38 Units / Rail
MC74HC573ADWG SOIC−WIDE

38 Units / Rail

(Pb−Free)
MC74HC573ADWR2 SOIC−WIDE 1000 Units / Reel
MC74HC573ADWR2G SOIC−WIDE

1000 Units / Reel

(Pb−Free)
MC74HC573ADT TSSOP−20* 75 Units / Rail
MC74HC573ADTR2 TSSOP−20* 2500 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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