MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull–up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock
drivers, and other bus–oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 124 FETs or 31 Equivalent Gates
20
20
DW SUFFIX
CASE 751D
1
PDIP–20
N SUFFIX
CASE 783
1
SO–20
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MARKING
DIAGRAMS
MC74HC540AN
AWLYYWW
HC540A
AWLYYWW
V
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
CC
1920 18 17 16 15 14
21 34567
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
13
12
11
9
8
10
Figure 1. Pinout: 20–Lead Packages (Top View)
FUNCTION TABLE
Inputs
OE1 OE2 A
L
L
L
L
H
X
X
H
Z = High Impedance
X = Don’t Care
Output Y
L
H
X
X
H
L
Z
Z
20
1
TSSOP–20
DT SUFFIX
CASE 948E
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW= Work Week
HC540A
ALYW
ORDERING INFORMATION
Device Package Shipping
MC74HC540AN PDIP–20 1440/Box
MC74HC540ADW SOIC–WIDE 38/Rail
MC74HC540ADT
MC74HC540ADTR2
SOIC–WIDEMC74HC540ADWR2
TSSOP–20 75/Rail
TSSOP–20 2500/Reel
1000/Reel
Semiconductor Components Industries, LLC, 2001
June, 2001 – Rev. 8
1 Publication Order Number:
MC74HC540A/D
MC74HC540A
Data
Inputs
Output
Enables
A1
A2
A3
A4
A5
A6
A7
A8
OE1
OE2
2
3
4
5
6
7
8
9
1
19
Figure 2. Logic Diagram
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
13
Y6
12
Y7
11
Y8
PIN 20 = V
PIN 10 = GND
CC
Inverting
Outputs
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2
MC74HC540A
Î
Î
Î
Î
Î
MAXIMUM RATINGS (Note 1.)
Symbol Parameter Value Unit
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
JA
P
D
MSL Moisture Sensitivity Level 1
F
R
V
ESD
I
LATCH–UP
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–rated
conditions is not implied.
2. IO absolute maximum rating must be observed.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
DC Supply Voltage 0.5 to 7.0 V
DC Input Voltage 0.5 to VCC 0.5 V
DC Output Voltage (Note 2.) 0.5 VO VCC 0.5 V
DC Input Diode Current 20 mA
DC Output Diode Current 35 mA
DC Output Sink Current 35 mA
DC Supply Current per Supply Pin 75 mA
DC Ground Current per Ground Pin 75 mA
Storage Temperature Range 65 to 150 C
Lead Temperature, 1 mm from Case for 10 Seconds 260 C
Junction Temperature Under Bias 150 C
Thermal Resistance PDIP
SOIC
TSSOP
Power Dissipation in Still Air at 85C PDIP
SOIC
TSSOP
67
96
128
750
500
450
C/W
mW
Flammability Rating Oxygen Index: 30% – 35% UL–94–VO (0.125 in)
ESD Withstand Voltage Human Body Model (Note 3.)
Machine Model (Note 4.)
Charged Device Model (Note 5.)
2000
200
1000
V
Latch–Up Performance Above VCC and Below GND at 85C (Note 6.) 300 mA
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
Vin, V
T
A
tr, t
f
ÎÎ
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3) VCC = 2.0 V
ООООООООООООООООООО
VCC = 4.5 V
VCC = 6.0 V
7. Unused inputs may not be left open. All inputs must be tied to a high– or low–logic input voltage level.
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3
2.0
0
55
0
0
0
ÎÎÎ
6.0
V
CC
125
1000
500
400
ÎÎ
V
V
C
ns
Î
MC74HC540A
V
CC
V
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Condition
V
V
V
V
I
in
I
OZ
I
CC
8. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Minimum High–Level Input Voltage V
IH
Maximum Low–Level Input Voltage V
IL
Minimum High–Level Output Voltage Vin = V
OH
Maximum Low–Level Output Voltage Vin = V
OL
Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 A
Maximum Three–State Leakage
Current
Maximum Quiescent Supply
Current (per Package)
= 0.1 V
out
|I
| ≤ 20 A
out
= VCC – 0.1 V
out
|I
| ≤ 20 A
out
IL
|I
| ≤ 20 A
out
Vin = V
IL
IH
|I
| ≤ 20 A
out
Vin = V
IH
Output in High Impedance State
Vin = VIL or V
V
= VCC or GND
out
Vin = VCC or GND
I
= 0 A
out
|I
| ≤ 3.6 mA
out
|I
| ≤ 6.0 mA
out
|I
| ≤ 7.8 mA
out
|I
| ≤ 3.6 mA
out
|I
| ≤ 6.0 mA
out
|I
| ≤ 7.8 mA
out
IH
–55 to 25°C ≤85°C ≤125°C Unit
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0 ±0.5 ±5.0 ±10.0 A
6.0 4 40 160 A
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
2.20
3.70
5.20
0.40
0.40
0.40
1.9
4.4
5.9
0.1
0.1
0.1
V
V
V
V
AC CHARACTERISTICS (C
Symbol Parameter
t
,
PLH
t
PHL
t
PLZ
t
PHZ
t
PZL
t
PZH
t
TLH
t
THL
C
C
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
C
10. Used to determine the no–load dynamic power consumption: PD = CPD V
Semiconductor High–Speed CMOS Data Book (DL129/D).
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
,
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
Maximum Input Capacitance 10 10 10 pF
in
Maximum Three–State Output Capacitance (Output in High Impedance State) 15 15 15 pF
out
PD
Power Dissipation Capacitance (Per Buffer) (Note 10.)
= 50 pF, Input tr = tf = 6 ns)
L
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
2
f + ICC VCC. For load considerations, see the ON
CC
Guaranteed Limit
–55 to 25°C ≤85°C ≤125°C Unit
80
30
18
15
110
45
25
21
110
45
25
21
60
22
12
10
35
100
40
23
20
140
60
31
26
140
60
31
26
75
28
15
13
120
55
28
25
165
75
38
31
165
75
38
31
90
34
18
15
ns
ns
ns
ns
pF
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4
t
r
INPUT A
t
PHL
OUTPUT Y
90%
50%
10%
90%
50%
10%
t
THL
Figure 3. Switching Waveform
MC74HC540A
V
t
f
V
CC
GND
t
PLH
t
TLH
OE1 or OE2
t
OUTPUT Y
OUTPUT Y
PZL
t
PZH
50%
50%
50%
t
PLZ
t
PHZ
50%
10%
90%
Figure 4. Switching Waveform
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
*Includes all probe and jig capacitance
CL*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
*Includes all probe and jig capacitance
1kΩ
CL*
Figure 5. Test Circuit Figure 6. Test Circuit
To 7 Other Inverters
One of Eight
Inverters
INPUT A
OE1
V
CC
OUTPUT Y
CONNECT TO VCC WHEN
TESTING t
CONNECT TO GND WHEN
TESTING t
PLZ
PHZ
AND t
and t
PZL
PZH
.
.
OE2
Figure 7. Logic Detail
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
Output enables (active–low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
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device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
high–impedance outputs.
5
–T–
SEATING
PLANE
MC74HC540A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
–A–
20
1
E
11
10
N
FG
D
20 PL
0.25 (0.010) T
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
B
C
K
M
M
A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
L
J
20 PL
0.25 (0.010) T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
M
E
F
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
M
M
B
MILLIMETERSINCHES
1.27 BSC0.050 BSC
1.27 1.770.050 0.070
H10X
M
B
M
0.25
D
20
1
B20X
M
SAS
T
0.25
18X
e
A
11
E
10
h X 45
B
B
A
SEATING
PLANE
A1
T
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
DIM MIN MAX
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
L
C
h 0.25 0.75
L 0.50 0.90
0 7
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6
MC74HC540A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
U
S
B
–U–
ISSUE A
S
JJ1
N
SECTION N–N
N
F
DETAIL E
DETAIL E
K
K1
0.25 (0.010)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
INCHES
6.60 0.260
–W–
MILLIMETERS
DIMAMIN MAX MIN MAX
6.40 0.252
B 4.30 4.50 0.169 0.177
C 1.20 0.047
--- ---
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
20X REFK
S
U0.15 (0.006) T
2X
L/2
L
PIN 1
IDENT
110
S
U0.15 (0.006) T
0.10 (0.004) V
M
T
1120
A
–V–
C
D
G
H
0.100 (0.004)
SEATING
–T–
PLANE
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7
MC74HC540A
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC74HC540A/D
8
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