ON Semiconductor MC74HC4051A, MC74HC4052A, MC74HC4053A Technical data

MC74HC4051A, MC74HC4052A, MC74HC4053A

Analog Multiplexers / Demultiplexers

High−Performance Silicon−Gate CMOS

The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE).

The HC4051A, HC4052A and HC4053A are identical in pinout to the metal−gate MC14051AB, MC14052AB and MC14053AB. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.

The Channel−Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs.

These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal−gate CMOS analog switches.

For a multiplexer/demultiplexer with injection current protection, see HC4851A and HC4852A.

Features

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (V

• Digital (Control) Power Supply Range (V

• Improved Linearity and Lower ON Resistance Than Metal−Gate

Counterparts

• Low Noise

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates

HC4052A — 168 FETs or 42 Equivalent Gates HC4053A — 156 FETs or 39 Equivalent Gates

• Pb−Free Packages are Available*

− VEE) = 2.0 to 12.0 V

CC

− GND) = 2.0 to 6.0 V

CC

16

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MARKING

DIAGRAMS

16

PDIP−16

N SUFFIX

1

A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location)

CASE 648

SOIC−16

D SUFFIX

CASE 751B

SOIC−16 WIDE

DW SUFFIX CASE 751G

TSSOP−16 DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX CASE 966

MC74HC405xAN

AWLYYWWG

1

16

HC405xAG

AWLYWW

1

16

AWLYWWG

1

16

1

16

74HC405xA

1

HC405xA

HC40

5xA

ALYWG

G

ALYWG

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

June, 2005 − Rev. 3

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.

MC74HC4051A/D

MC74HC4051A, MC74HC4052A, MC74HC4053A

FUNCTION TABLE − MC74HC4051A

Single−Pole, 8−Position Plus Common Off

ANALOG

INPUTS/

OUTPUTS

CHANNEL

SELECT

INPUTS

Double−Pole, 4−Position Plus Common Off

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

ENABLE

X0

X1

X2

X3

Y0

Y1

Y2

Y3

ENABLE

LOGIC DIAGRAM

MC74HC4051A

13

X0

14

X1

15

X2

12

X3

1

X4

5

X5

2

X6

4

X7

11

A

10

B

9

C

6

PIN 16 = V PIN 7 = V PIN 8 = GND

LOGIC DIAGRAM

MC74HC4052A

12

14

15

11

1

5

2

4

10

A

9

B

6

MULTIPLEXER/

DEMULTIPLEXER

CC

EE

X SWITCH

Y SWITCH

3

X

13

X

3

Y

PIN 16 = V PIN 7 = V

EE

PIN 8 = GND

COMMON OUTPUT/ INPUT

COMMON OUTPUTS/INPUTS

CC

Control Inputs

Select

CBA

L

L L L L L L L L

H

L

H

L

H

L

H

L

H

X

ON ChannelsEnable

L H L H L H L H X

X0 X1 X2 X3 X4 X5 X6 X7

NONE

X = Don’t Care

Pinout: MC74HC4051A (Top View)

V

X2 X1 X0 X3 A B C

CC

1516 14 13 12 11 10

21 34567

X4 X6 X X7 X5 Enable VEEGND

FUNCTION TABLE − MC74HC4052A

Control Inputs

Select

BA

L

L L L L

H

H H X

L

H

L H X

ON ChannelsEnable

Y0 Y1 Y2 Y3

NONE

X = Don’t Care

Pinout: MC74HC4052A (Top View)

V

X2 X1 X X0 X3 A B

CC

1516 14 13 12 11 10

9

8

X0 X1 X2 X3

9

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2

21 34567

8

Y0 Y2 Y Y3 Y1 Enable VEEGND

MC74HC4051A, MC74HC4052A, MC74HC4053A

Î

LOGIC DIAGRAM

MC74HC4053A

Triple Single−Pole, Double−Position Plus Common Off

12

X0

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

X1

Y0

Y1

ENABLE

13

2

1

5

Z0

3

Z1

11

A

10

B

9

C

6

X SWITCH

Y SWITCH

Z SWITCH

NOTE: This device allows independent control of each switch. Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch and Input C controls the Z−Switch

14

X

15

Y

4

Z

PIN 16 = V PIN 7 = V

EE

PIN 8 = GND

CC

COMMON OUTPUTS/INPUTS

FUNCTION TABLE − MC74HC4053A

Control Inputs

Select

CBA

L

L L L L L L L L

H

L

H

L

H

L

H

L

H

X

ON ChannelsEnable

L

Z0

H

Z0

L

Z0

H

Z0

L

Z1

H

Z1

L

Z1

H

Z1

X

X = Don’t Care

Pinout: MC74HC4053A (Top View)

V

YXX1X0ABC

CC

1516 14 13 12 11 10

Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1

NONE

X0 X1 X0 X1 X0 X1 X0 X1

9

21 34567

8

Y1 Y0 Z1 Z Z0 Enable VEEGND

MAXIMUM RATINGS

Symbol

V

ÎÎ

V

ÎÎ

Positive DC Supply Voltage (Referenced to GND)

CC

EE

V

I

P

T

stg

T

ОООООООООООО

Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage

IS

ОООООООООООО

Digital Input Voltage (Referenced to GND)

in

DC Current, Into or Out of Any Pin Power Dissipation in Still Air, Plastic DIP†

D

ОООООООООООО

Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

Parameter

(Referenced to VEE)

EIAJ/SOIC Package†

TSSOP Package†

Plastic DIP, SOIC or TSSOP Package

Value

– 0.5 to + 7.0

ÎÎÎ

– 0.5 to + 14.0

– 7.0 to + 5.0

VEE − 0.5 to

VCC + 0.5

ÎÎÎ

– 0.5 to VCC + 0.5

± 25

750 500

ÎÎÎ

450

– 65 to + 150

260

ÎÎÎ

Unit

Î

mA

mW

Î

_C _C

This device contains protection

V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must

V V

be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and V

V

should be constrained to the

out

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

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MC74HC4051A, MC74HC4052A, MC74HC4053A

Î

l

RECOMMENDED OPERATING CONDITIONS

Symbol

V

ÎÎ

V

Positive DC Supply Voltage (Referenced to GND)

CC

ОООООООООООО

Negative DC Supply Voltage, Output (Referenced to

EE

GND)

V

Analog Input Voltage

IS

V

Digital Input Voltage (Referenced to GND)

in

VIO*

ÎÎ

T

tr, t

Static or Dynamic Voltage Across Switch Operating Temperature Range, All Package Types

A

Input Rise/Fall Time VCC = 2.0 V

f

(Channel Select or Enable Inputs) VCC = 3.0 V

ОООООООООООО

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

Parameter

(Referenced to VEE)

VCC = 4.5 V VCC = 6.0 V

Min

2.0

Î

− 6.0

V

EE

GND

– 55

0 0

Î

0

Î

0

Max

6.0

12.0

Î

GND

V

CC

V

CC

1.2

+ 125

1000

600

Î

500

Î

400

Unit

V

Î

V

V V V

_C

ns

Î

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) V

Symbo

V

IH

V

IL

I

in

I

CC

Minimum High−Level Input Voltage, Channel−Select or Enable Inputs

Maximum Low−Level Input Voltage, Channel−Select or Enable Inputs

Maximum Input Leakage Current, Channel−Select or Enable Inputs

Maximum Quiescent Supply Current (per Package)

Parameter Condition

Ron = Per Spec 2.0

Vin = VCC or GND, VEE = − 6.0 V

Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = − 6.0

= GND, Except Where Noted

EE

V

CC

V

3.0

4.5

6.0

3.0

4.5

6.0

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

6.0 ± 0.1 ± 1.0 ± 1.0

6.0

1

4

10 40

1.50

2.10

3.15

4.20

0.5

0.9

1.35

1.8

20 80

Unit

V

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor H igh−Speed C MOS D ata B ook ( DL129/D).

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MC74HC4051A, MC74HC4052A, MC74HC4053A

l

DC CHARACTERISTICS — Analog Section

Guaranteed Limit

Symbo

R

on

DR

on

I

off

Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to

Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package

Maximum Off−Channel Leakage Current, Any One Channel

Parameter Condition V

VEE; IS ≤ 2.0 mA (Figures 1, 2)

Vin = VIL or VIH; VIS = VCC or

(Endpoints); IS ≤ 2.0 mA

V

EE

(Figures 1, 2) Vin = VIL or VIH;

VIS = 1/2 (VCC − VEE); IS ≤ 2.0 mA

Vin = VIL or VIH; VIO = VCC − VEE;

CC

4.5

6.0

4.5

6.0

4.5

6.0

6.0 − 6.0 0.1 0.5 1.0

Switch Off (Figure 3)

Maximum Off−ChannelHC4051A Leakage Current, HC4052A Common Channel HC4053A

I

Maximum On−ChannelHC4051A

on

Leakage Current, HC4052A Channel−to−Channel HC4053A

AC CHARACTERISTICS (C

Symbo

t

,

Maximum Propagation Delay, Channel−Select to Analog Output

PLH

t

(Figure 9)

PHL

t

,

Maximum Propagation Delay, Analog Input to Analog Output

PLH

t

(Figure 10)

PHL

t

,

Maximum Propagation Delay, Enable to Analog Output

PLZ

t

(Figure 11)

PHZ

t

,

Maximum Propagation Delay, Enable to Analog Output

PZL

t

(Figure 11)

PZH

C

Maximum Input Capacitance, Channel−Select or Enable Inputs 10 10 10 pF

in

C

Maximum Capacitance Analog I/O 35 35 35 pF

I/O

= 50 pF, Input tr = tf = 6 ns)

L

Vin = VIL or VIH; VIO = VCC − VEE; Switch Off (Figure 4)

Vin = VIL or VIH; Switch−to−Switch = VCC − VEE; (Figure 5)

Parameter

6.0

(All Switches Off) Common O/I: HC4051A

HC4052A HC4053A

Feedthrough 1.0 1.0 1.0

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High−Speed CMOS Data Book (DL129/D)

C

Power Dissipation Capacitance (Figure 13)* HC4051A

PD

HC4052A HC4053A

*Used to determine t he no−load dynamic p ower consumption: PD = CPD V

2

f + ICC VCC. For load considerations, see C hapter 2 o f t h e

CC

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

−55 to 25°C ≤85°C ≤125°C

V

EE

0.0

− 4.5

− 6.0

0.0

− 4.5

− 6.0

0.0

− 4.5

− 6.0

V

CC

V

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

2.0

3.0

4.5

6.0

190 120 100

150 100

80 30

12 10

0.2

0.1

0.2

0.1

240 150 125

190 125 100

35 15 12

2.0

1.0

2.0

1.0

280 170 140

230 140 115

40 18 14

4.0

2.0

4.0

2.0

Guaranteed Limit

−55 to 25°C ≤85°C ≤125°C

270

90 59 45

40 25 12 10

160

70 48 39

245 115

49 39

130

80 50

320 110

79 65

60 30 15 13

200

95 63 55

315 145

69 58

130

80 50

350 125

85 75

70 32 18 15

220 110

76 63

345 155

83 67

130

80 50

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

45 80 45

Unit

W

mA

Unit

ns

pF

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MC74HC4051A, MC74HC4052A, MC74HC4053A

l

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbo

BW Maximum On−Channel Bandwidth

or Minimum Frequency Response (Figure 6)

− Off−Channel Feedthrough Isolation (Figure 7)

− Feedthrough Noise. Channel−Select Input to Common I/O (Figure 8)

− Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051A)

THD Total Harmonic Distortion

(Figure 14)

*Limits not tested. Determined by design and verified by qualification.

Parameter Condition

fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS; Increase f Frequency Until dB Meter Reads −3dB; RL = 50W, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

IS

fin = 10kHz, RL = 600W, CL = 50pF

fin = 1.0MHz, RL = 50W, CL = 10pF

Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600W, CL = 50pF

RL = 10kW, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

IS

fin = 10kHz, RL = 600W, CL = 50pF

fin = 1.0MHz, RL = 50W, CL = 10pF

fin = 1kHz, RL = 10kW, CL = 50pF THD = THD

measured

VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave

VIS = 11.0VPP sine wave

− THD

source

V

in

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

2.25

4.50

6.00

V

CC

V

EE

V

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

−2.25

−4.50

−6.00

Limit*

25°C

‘51 ‘52 ‘53

80

95 95 95

120 120 120

80 80

−50

−40

−40 25

105 135

35

145 190

−50

−60

Unit

MHz

dB

mV

dB

PP

%

2.25

4.50

6.00

−2.25

−4.50

−6.00

0.10

0.08

0.05

300

250

180

160

140

200

150

100

, ON RESISTANCE (OHMS)

on

R

50

125°C

25°C

−55 °C

120

100

80

60

, ON RESISTANCE (OHMS)

on

40

R

20

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

EE

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25

2.0

VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V

2.5 2.75 3.0

EE

Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V Figure 1b. Typical On Resistance, VCC − VEE = 3.0 V

125°C

25°C

−55 °C

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