MC74HC374A
2
Octal 3−State Non−Inverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The MC74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
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MARKING
DIAGRAMS
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374A is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
0
1
PDIP−20
N SUFFIX
CASE 738
20
MC74HC374AN
AWLYYWWG
1
device is similar in function to the HC534A which has inverting
outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
20
20
SOIC−20
DW SUFFIX
1
CASE 751D
74HC374A
AWLYYWWG
1
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
• Pb−Free Packages are Available*
20
TSSOP−20
DT SUFFIX
1
CASE 948E
20
HC
374A
ALYWG
G
1
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 10
1 Publication Order Number:
20
20
1
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
SOEIAJ−20
F SUFFIX
CASE 967
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
74HC374A
AWLYWWG
1
MC74HC374A/D
D0
D1
D2
DATA
INPUTS
OUTPUT ENABLE
D3
D4
D5
D6
D7
CLOCK
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
11
1
2
5
6
9
12
15
16
19
MC74HC374A
Q0
Q1
Q2
Q3
NONINVERTING
Q4
Q5
Q6
Q7
OUTPUTS
PIN 20 = V
PIN 10 = GND
CC
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
D0
D1
Q1 5
Q2
D2
D3
Q3
GND
1
2
3
4
6
7
8
9
10
20
V
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
11
CLOCK
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
LHH
LLL
L L,H, X No Change
HXXZ
X = don’t care
Z = high impedance
ORDERING INFORMATION
Device Package Shipping
MC74HC374AN PDIP−20 18 Units / Box
MC74HC374ANG PDIP−20
(Pb−Free)
MC74HC374ADW SOIC−20 WIDE 38 Units / Rail
MC74HC374ADWG SOIC−20 WIDE
(Pb−Free)
MC74HC374ADWR2 SOIC−20 WIDE 1000 Tape & Reel
MC74HC374ADWR2G SOIC−20 WIDE
(Pb−Free)
MC74HC374ADT TSSOP−20* 75 Units / Rail
MC74HC374ADTG TSSOP−20* 75 Units / Rail
MC74HC374ADTR2 TSSOP−20* 2500 Tape & Reel
MC74HC374ADTR2G TSSOP−20* 2500 Tape & Reel
MC74HC374AF SOEIAJ−20 40 Units / Rail
MC74HC374AFG SOEIAJ−20
(Pb−Free)
MC74HC374AFEL SOEIAJ−20 2000 Tape & Reel
MC74HC374AFELG SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
18 Units / Box
38 Units / Rail
1000 Tape & Reel
40 Units / Rail
2000 Tape & Reel
†
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2
MC74HC374A
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MAXIMUM RATINGS
Symbol
V
V
ÎÎ
ÎÎ
DC Supply Voltage (Referenced to GND)
CC
V
DC Input Voltage (Referenced to GND)
in
DC Output Voltage (Referenced to GND)
out
I
DC Input Current, per Pin
in
I
DC Output Current, per Pin
out
I
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, Plastic DIP†
D
ОООООООООООО
T
Storage Temperature
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
(Plastic DIP, SOIC, SSOP or TSSOP Package)
ОООООООООООО
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
Parameter
SOIC Package†
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
± 35
± 75
750
500
ÎÎÎ
450
– 65 to + 150
260
ÎÎÎ
Unit
mW
Î
Î
V
V
V
mA
mA
mA
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, V
should be constrained to the
V
out
range GND v (V
in
or V
) v VCC.
out
in
and
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
Unused outputs must be left open.
).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
Vin, V
T
A
tr, t
f
ÎÎ
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) V
ОООООООООООО
Parameter
CC
V
CC
= 4.5 V
= 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎ
Symbo
V
ÎÎ
ÎÎ
V
ÎÎ
ÎÎ
V
OH
ÎÎ
ÎÎ
ÎÎ
V
OL
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ОООООООО
Parameter
Minimum High−Level Input Voltage
IH
ОООООООО
ОООООООО
Maximum Low−Level Input Voltage
IL
ОООООООО
ОООООООО
Minimum High−Level Output
Voltage
ОООООООО
ОООООООО
ОООООООО
Maximum Low−Level Output
ОООООООО
Voltage
ОООООООО
ОООООООО
ОООООООО
ООООООО
Test Conditions
V
= 0.1 V or VCC – 0.1 V
out
ООООООО
|I
| v 20 mA
out
ООООООО
V
= 0.1 V or VCC – 0.1 V
out
ООООООО
|I
| v 20 mA
out
ООООООО
Vin = VIH or V
|I
| v 20 mA
out
ООООООО
Vin = VIH or V
ООООООО
Vin = VIH or V
ООООООО
|I
| v 20 mA
out
ООООООО
Vin = VIH or V
ООООООО
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Min
2.0
0
– 55
0
0
Î
0
IL
IL|Iout
|I
out
|I
out
IL
IL|Iout
|I
out
|I
out
3
Max
6.0
V
CC
+ 125
1000
500
Î
400
| v 2.4 mA
| v 6.0 mA
| v 7.8 mA
| v 2.4 mA
| v 6.0 mA
| v 7.8 mA
Unit
Î
Î
V
V
2.0
Î
3.0
4.5
Î
6.0
2.0
Î
3.0
4.5
Î
6.0
2.0
4.5
Î
6.0
3.0
Î
4.5
6.0
2.0
Î
4.5
6.0
Î
3.0
4.5
Î
6.0
_C
CC
V
V
ns
Guaranteed Limit
– 55 to
25_C
1.50
ÎÎ
2.10
3.15
ÎÎ
4.20
0.50
ÎÎ
0.90
1.35
ÎÎ
1.80
1.90
4.40
ÎÎ
5.90
2.48
ÎÎ
2.98
5.48
0.10
ÎÎ
0.10
0.10
ÎÎ
0.26
0.26
ÎÎ
0.26
v 85_C
1.50
ÎÎ
2.10
3.15
ÎÎ
4.20
0.50
ÎÎ
0.90
1.35
ÎÎ
1.80
1.90
4.40
ÎÎ
5.90
2.34
ÎÎ
3.84
5.34
0.10
ÎÎ
0.10
0.10
ÎÎ
0.33
0.33
ÎÎ
0.33
v 125_C
1.50
ÎÎ
2.10
3.15
ÎÎ
4.20
0.50
ÎÎ
0.90
1.35
ÎÎ
1.80
1.90
4.40
ÎÎ
5.90
2.20
ÎÎ
3.70
5.20
0.10
ÎÎ
0.10
0.10
ÎÎ
0.40
0.40
ÎÎ
0.40
Unit
V
V
V
V
V
V
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