MC74HC373A
2
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
0
1
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20
PDIP−20
N SUFFIX
CASE 738
1
MARKING
DIAGRAMS
MC74HC373AN
AWLYYWWG
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
Features
20
20
SOIC−20
DW SUFFIX
1
CASE 751D
74HC373A
AWLYYWWG
1
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
20
TSSOP−20
DT SUFFIX
1
CASE 948E
20
HC
373A
ALYWG
G
1
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 12
1 Publication Order Number:
20
20
1
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
SOEIAJ−20
F SUFFIX
CASE 967
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
74HC373A
AWLYWWG
1
MC74HC373A/D
MC74HC373A
PIN ASSIGNMENT
D0
D1
D2
DATA
INPUTS
LATCH ENABLE
OUTPUT ENABLE
D3
D4
D5
D6
D7
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
PIN 20 = V
PIN 10 = GND
NONINVERTING
OUTPUTS
CC
OUTPUT
ENABLE
Q0
D0
D1
Q1 5
Q2
D2
D3
Q3
GND
1
2
3
4
6
7
8
9
10
20
V
CC
19
Q7
18
D7
17
D6
16
Q6
15
Q5
14
D5
13
D4
12
Q4
LATCH
11
ENABLE
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
LHHH
LHLL
L L X No Change
HXXZ
X = Don’t Ca r e
Z = High Impedance
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
46.5
1.5
5.0
0.0075
Units
ea
ns
mW
pJ
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MC74HC373A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
MAXIMUM RATINGS
Symbol
V
V
ÎÎ
ÎÎ
DC Supply Voltage (Referenced to GND)
CC
V
DC Input Voltage (Referenced to GND)
in
DC Output Voltage (Referenced to GND)
out
I
DC Input Current, per Pin
in
I
DC Output Current, per Pin
out
I
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, Plastic DIP†
D
ОООООООООООО
ОООООООООООО
T
Storage Temperature
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
(Plastic DIP, SOIC, SSOP or TSSOP Package)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
Vin, V
T
tr, t
ÎÎ
ÎÎ
DC Supply Voltage (Referenced to GND)
CC
DC Input Voltage, Output Voltage (Referenced to GND)
out
Operating Temperature, All Package Types
A
Input Rise and Fall Time VCC = 2.0 V
f
ОООООООООООО
(Figure 1) VCC = 4.5 V
ОООООООООООО
Parameter
Parameter
SOIC Package†
TSSOP Package†
VCC = 6.0 V
Value
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
± 35
± 75
750
ÎÎÎ
500
450
ÎÎÎ
– 65 to + 150
260
Min
2.0
– 55
Î
Î
Max
6.0
0
V
CC
+ 125
0
1000
Î
0
500
0
400
Î
Unit
mA
mA
mA
mW
Î
Î
Unit
V
V
_C
ns
Î
Î
_C
_C
This device contains protection
V
V
V
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
) v VCC.
out
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
ORDERING INFORMATION
Device Package Shipping
MC74HC373AN PDIP−20 18 Units / Box
MC74HC373ANG PDIP−20
18 Units / Box
(Pb−Free)
MC74HC373ADW SOIC−20 WIDE 38 Units / Rail
MC74HC373ADWG SOIC−20 WIDE
38 Units / Rail
(Pb−Free)
MC74HC373ADWR2 SOIC−20 WIDE 1000 Units / Reel
MC74HC373ADWR2G SOIC−20 WIDE
1000 Units / Reel
(Pb−Free)
MC74HC373ADT TSSOP−20* 75 Units / Rail
MC74HC373ADTG TSSOP−20* 75 Units / Rail
MC74HC373ADTR2 TSSOP−20* 2500 Units / Reel
MC74HC373ADTR2G TSSOP−20* 2500 Units / Reel
MC74HC373AF SOEIAJ−20 40 Units / Rail
MC74HC373AFG SOEIAJ−20
40 Units / Rail
(Pb−Free)
MC74HC373AFEL SOEIAJ−20 2000 Units / Reel
MC74HC373AFELG SOEIAJ−20
2000 Units / Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
†
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