ON Semiconductor MC74HC373A Technical data

MC74HC373A

Octal 3−State Non−Inverting Transparent Latch

High−Performance Silicon−Gate CMOS

The MC74HC373A is identical in pinout to the LS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high−impedance state. Thus, data may be latched even when the

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PDIP−20 N SUFFIX CASE 738

MARKING

DIAGRAMS

MC74HC373AN

AWLYYWWG

outputs are not enabled.

The HC373A is identical in function to the HC573A which has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HC373A is the non−inverting version of the HC533A.

Features

SOIC−20

DW SUFFIX

CASE 751D

74HC373A

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• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the JEDEC Standard No. 7.0 A Requirements

• Chip Complexity: 186 FETs or 46.5 Equivalent Gates

TSSOP−20 DT SUFFIX

CASE 948E

373A

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• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

July, 2005 − Rev. 12

1 Publication Order Number:

See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.

SOEIAJ−20

F SUFFIX

CASE 967

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location)

ORDERING INFORMATION

74HC373A

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MC74HC373A/D

MC74HC373A

PIN ASSIGNMENT

DATA

INPUTS

LATCH ENABLE

OUTPUT ENABLE

LOGIC DIAGRAM

PIN 20 = V PIN 10 = GND

NONINVERTING

OUTPUTS

OUTPUT

ENABLE

Q1 5

GND

LATCH

ENABLE

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change

HXXZ

X = Don’t Ca r e Z = High Impedance

Design Criteria

Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product

*Equivalent to a two−input NAND gate.

Value

46.5

1.5

5.0

0.0075

Units

ea ns

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MC74HC373A

MAXIMUM RATINGS

Symbol

ÎÎ

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

out

DC Input Current, per Pin

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

Power Dissipation in Still Air, Plastic DIP†

ОООООООООООО

Storage Temperature

stg

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Vin, V

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types

Input Rise and Fall Time VCC = 2.0 V

ОООООООООООО

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

SOIC Package†

TSSOP Package†

VCC = 6.0 V

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750

ÎÎÎ

500 450

ÎÎÎ

– 65 to + 150

260

Min

2.0

– 55

Max

6.0

+ 125

1000

500

400

Unit

mA mA mA

Unit

V _C ns

_C _C

This device contains protection V V V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

) v VCC.

out

Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

ORDERING INFORMATION

Device Package Shipping

MC74HC373AN PDIP−20 18 Units / Box MC74HC373ANG PDIP−20

18 Units / Box

(Pb−Free) MC74HC373ADW SOIC−20 WIDE 38 Units / Rail MC74HC373ADWG SOIC−20 WIDE

38 Units / Rail

(Pb−Free) MC74HC373ADWR2 SOIC−20 WIDE 1000 Units / Reel MC74HC373ADWR2G SOIC−20 WIDE

1000 Units / Reel

(Pb−Free) MC74HC373ADT TSSOP−20* 75 Units / Rail MC74HC373ADTG TSSOP−20* 75 Units / Rail MC74HC373ADTR2 TSSOP−20* 2500 Units / Reel MC74HC373ADTR2G TSSOP−20* 2500 Units / Reel MC74HC373AF SOEIAJ−20 40 Units / Rail MC74HC373AFG SOEIAJ−20

40 Units / Rail

(Pb−Free) MC74HC373AFEL SOEIAJ−20 2000 Units / Reel MC74HC373AFELG SOEIAJ−20

2000 Units / Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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