ON Semiconductor MC74AC74, MC74ACT74 Technical data

MC74AC74, MC74ACT74

Dual D−Type Positive
Edge−Triggered Flip−Flop

The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.

Asynchronous Inputs:

LOW input to SD (Set) sets Q to HIGH level

LOW input to CD (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q and Q HIGH

Features

• Outputs Source/Sink 24 mA

• ′ACT74 Has TTL Compatible Inputs

• Pb−Free Packages are Available

V

CD2D2CP2SD2Q2Q

CC

1314 12 11 10 9 8

C

D1

Q

D

1

1

CP

Q

S

1

1

D1

CP

2

D

2

S

D2

Q
Q

C

D2

2

2

2

http://onsemi.com

PDIP−14

N SUFFIX

14

1

14

1

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

14

1

DT SUFFIX

CASE 948G

SOEIAJ−14

14

1

M SUFFIX
CASE 965

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.

21 34567

C

D1D1

CP1SD1Q1Q

GND

1

Figure 1. Pinout: 14−Lead Packages Conductors

(Top View)

PIN ASSIGNMENT

PIN FUNCTION

D1, D

2

CP1, CP

CD1, C

SD1, S

2

D2

D2

Q1, Q1, Q2,
Q

2

© Semiconductor Components Industries, LLC, 2006

October, 2006 − Rev. 7

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

1 Publication Order Number:

MC74AC74/D

TRUTH TABLE (Each Half)

Inputs Outputs

S

D

L H X X H L

H L X X L H

L L X X H H
H H H H L
H H L L H
H H L X Q

NOTE: H = HIGH Voltage Level

C

D

CP D Q Q

0

L = LOW Voltage Level
X = Immaterial;

= LOW-to-HIGH Clock Transition

Q0(Q0) = Previous Q(Q) before LOW-to-HIGH

Transition of Clock

S

D

MC74AC74, MC74ACT74

Q

0

Q

S

D1

D

S

D2

D2CP

1

1

Q

2

CP

Q

1

C

D1

1

Q

2

CD

2

2

Figure 2. Logic Symbol

D

Q

CP

Q

C

D

NOTE: This diagram is provided only for the understanding of

logic operations and should not be used to estimate
propagation delays.

Figure 3. Logic Diagram

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

in

V

out

I

in

I

out

I

CC

T

stg

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V

DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V

DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V

DC Input Current, per Pin ±20 mA

DC Output Sink/Source Current, per Pin ±50 mA

DC VCC or GND Current per Output Pin ±50 mA

Storage Temperature −65 to +150 °C

http://onsemi.com

2

MC74AC74, MC74ACT74

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

V

CC

Vin, V

tr, t

f

tr, t

f

T

J

T

A

I

OH

I

OL

out

Supply Voltage

DC Input Voltage, Output Voltage (Ref. to GND) 0 − V

Input Rise and Fall Time (Note )
′AC Devices except Schmitt Inputs

Input Rise and Fall Time (Note )
′ACT Devices except Schmitt Inputs

Junction Temperature (PDIP) − − 140 °C

Operating Ambient Temperature Range −40 25 85 °C

Output Current − High − − −24 mA

Output Current − Low − − 24 mA

1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

DC CHARACTERISTICS

V

Symbol Parameter

V

IH

Minimum High Level
Input Voltage

V

IL

Maximum Low Level
Input Voltage

V

OH

Minimum High Level
Output Voltage

V

OL

Maximum Low Level
Output Voltage

I

IN

Maximum Input
Leakage Current

I

OLD

I

OHD

I

CC

†Minimum Dynamic

Output Current

Maximum Quiescent
Supply Current

*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.

NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

CC

(V)

3.0 1.5 2.1 2.1 V

4.5 2.25 3.15 3.15 V or VCC − 0.1 V

5.5 2.75 3.85 3.85

3.0 1.5 0.9 0.9 V

4.5 2.25 1.35 1.35 V or VCC − 0.1 V

5.5 2.75 1.65 1.65

3.0 2.99 2.9 2.9

4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

3.0 − 2.56 2.46 −12 mA

4.5 − 3.86 3.76 I

5.5 − 4.86 4.76 −24 mA

3.0 0.002 0.1 0.1

4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

3.0 − 0.36 0.44 12 mA

4.5 − 0.36 0.44 I

5.5 − 0.36 0.44 24 mA

5.5 − ±0.1 ±1.0

5.5 − − 75 mA V

5.5 − − −75 mA V

5.5 − 4.0 40

′AC 2.0 5.0 6.0

′ACT 4.5 5.0 5.5

CC

VCC @ 3.0 V − 150 −

VCC @ 4.5 V − 40 − ns/V

VCC @ 5.5 V − 25 −

VCC @ 4.5 V − 10 −

VCC @ 5.5 V − 8.0 −

74AC 74AC

TA =

TA = +25°C

−40°C to

Unit Conditions

+85°C

Typ Guaranteed Limits

= 0.1 V

OUT

= 0.1 V

OUT

I

= −50 mA

OUT

*VIN = VIL or V

V

OH

I

OUT

−24 mA

= 50 mA

*VIN = VIL or V

mA

mA

V

OL

VI = VCC, GND

OLD

OHD

VIN = VCC or GND

24 mA

= 1.65 V Max

= 3.85 V Min

V

V

ns/V

IH

IH

http://onsemi.com

3

MC74AC74, MC74ACT74

AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

74AC 74AC

TA = −40°C

to +85°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Unit

MHz 3−3

ns 3−6

ns 3−6

ns 3−6

ns 3−6

Unit

ns 3−9

ns 3−9

ns 3−6

ns 3−9

Symbol Parameter

f

t

t

t

t

max

PLH

PHL

PLH

PHL

Maximum Clock
Frequency

Propagation Delay
CDn or SDn to Qn or Q

Propagation Delay
CDn or S

to Qn or Q

Dn

Propagation Delay
CPn to Qn or Q

n

Propagation Delay
CPn to Qn or Q

n

n

n

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

Voltage Range 5.0 V is 5.0 V ±0.5 V.

AC OPERATING REQUIREMENTS

Symbol Parameter

t

s

t

h

t

w

t

rec

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

Voltage Range 5.0 V is 5.0 V ±0.5 V.

Set-up Time, HIGH or LOW 3.3 1.5 4.0 4.5
Dn to CP

n

Hold Time, HIGH or LOW 3.3 −2.0 0.5 0.5
Dn to CP

CPn or CDn or S

n

Dn

Pulse Width 5.0 2.5 4.5 5.0

Recovery TIme 3.3 −2.5 0 0
CDn or SDn to CP 5.0 −2.0 0 0

VCC*

(V)

TA = +25°C
CL = 50 pF

Min Typ Max Min Max

3.3 100 125 − 95 −

5.0 140 160 − 125 −

3.3 5.0 8.0 12.5 4.0 13.0

5.0 3.5 6.0 9.0 3.0 10.0

3.3 4.0 10.5 12.0 3.5 13.5

5.0 3.0 8.0 9.5 2.5 10.5

3.3 4.5 8.0 13.5 4.0 16.0

5.0 3.5 6.0 10.0 3.0 10.5

3.3 3.5 8.0 14.0 3.5 14.5

5.0 2.5 6.0 10.0 2.5 10.5

74AC 74AC

VCC*

(V)

TA = +25°C
CL = 50 pF

Typ Guaranteed Minimum

5.0 1.0 3.0 3.0

5.0 −1.5 0.5 0.5

3.3 3.0 5.5 7.0

Fig.

No.

Fig.

No.

http://onsemi.com

4