ON Semiconductor MC74AC573, MC74ACT573 Technical data
MC74AC573, MC74ACT573
Octal Buffer/Line Driver
with 3−State Outputs
The MC74AC573/74ACT573 is a high−speed octal latch with
buffered common Latch Enable (LE) and buffered common Output
Enable (OE
The MC74AC573/74ACT573 is functionally identical to the
MC74AC373/74ACT373 but has inputs and outputs on opposite sides.
) inputs.
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Features
• Inputs and Outputs on Opposite Sides of Package Allowing Easy
Interface with Microprocessors
• Useful as Input or Output Port for Microprocessors
• Functionally Identical to MC74AC373/74ACT373
• 3−State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
• ′ACT573 Has TTL Compatible Inputs
• Pb−Free Packages are Available*
O
V
CC
0O1O2O3O4O5O6O7
1920 18 17 16 15 14
21 34567
OE
D0D1D2D3D4D5D6D7GND
13
8
Figure 1. Pinout 20−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN FUNCTION
D0−D
7
LE Latch Enable Input
OE 3−State Output Enable Input
O0−O
7
Data Inputs
3−State Latch Outputs
D0D1D2D3D4D5D6D
LE
OE
O
O
1O2O3O4O5O6O7
0
7
Figure 2. Logic Symbol
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LE
12
11
9
10
MARKING
DIAGRAM
20
1
PDIP−20
N SUFFIX
CASE 738
20
1
SO−20
DW SUFFIX
CASE 751D
20
1
TSSOP−20
DT SUFFIX
CASE 948E
20
1
EIAJ−20
M SUFFIX
CASE 967
xxx = AC or ACT
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
MC74xxx573N
AWLYYWWG
xxx573
AWLYYWWG
xxx
573
ALYW G
G
74xxx573
AWLYWWG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 7
1 Publication Order Number:
MC74AC573/D
MC74AC573, MC74ACT573
TRUTH TABLE
Inputs Outputs
OE LE D
L H H H
L H L L
L L X O
H X X Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
= Previous O0 before LOW−to−HIGH Transition of Clock
0
LE
D
1
D
Q
LE
D
0
D
LE
n
D
2
D
Q
LE
Functional Description
The MC74AC573/74ACT574 contains eight D−type
latches with 3−state output buffers. When the Latch Enable
O
n
(LE) input is HIGH, data on the D
inputs enters the latches.
n
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
0
on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state buffers are controlled by the
Output Enable (OE
enabled. When OE
) input. When OE is LOW, the buffers are
is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
D
3
D
Q
LE
D
4
D
Q
LE
D
5
D
Q
LE
D
6
D
Q
LE
D
7
D
Q
LE
Q
OE
O
0
NOTE: That this diagram is provided only for the understanding of logic
O
1
operations and should not be used to estimate propagation delays.
O
2
O
3
O
4
Figure 3. Logic Diagram
O
5
O
6
O
7
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MC74AC573, MC74ACT573
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
VIN, V
OUT
tr, t
f
tr, t
f
T
J
T
A
I
OH
I
OL
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V
DC Input Current, per Pin ±20 mA
DC Output Sink/Source Current, per Pin ±50 mA
DC VCC or GND Current per Output Pin ±50 mA
Storage Temperature −65 to +150 °C
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND) 0 − V
′AC 2.0 5.0 6.0
′ACT 4.5 5.0 5.5
CC
V
V
VCC @ 3.0 V − 150 −
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
VCC @ 4.5 V − 40 − ns/V
VCC @ 5.5 V − 25 −
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 4.5 V − 10 −
VCC @ 5.5 V − 8.0 −
ns/V
Junction Temperature (PDIP) − − 140 °C
Operating Ambient Temperature Range −40 25 85 °C
Output Current − High − − −24 mA
Output Current − Low − − 24 mA
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MC74AC573, MC74ACT573
DC CHARACTERISTICS
74AC 74AC
V
CC
Symbol Parameter
(V)
TA = +25°C
Typ Guaranteed Limits
V
IH
Minimum High Level
Input Voltage
3.0 1.5 2.1 2.1 V
4.5 2.25 3.15 3.15 V or VCC − 0.1 V
5.5 2.75 3.85 3.85
V
IL
Maximum Low Level
Input Voltage
3.0 1.5 0.9 0.9 V
4.5 2.25 1.35 1.35 V or VCC − 0.1 V
5.5 2.75 1.65 1.65
V
OH
Minimum High Level
Output Voltage
3.0 2.99 2.9 2.9
4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
3.0 − 2.56 2.46 −12 mA
4.5 − 3.86 3.76 I
5.5 − 4.86 4.76 −24 mA
V
OL
Maximum Low Level
Output Voltage
3.0 0.002 0.1 0.1
4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
3.0 − 0.36 0.44 12 mA
4.5 − 0.36 0.44 I
5.5 − 0.36 0.44 24 mA
I
IN
I
OZ
Maximum Input
Leakage Current
Maximum
3−State
5.5 − ±0.1 ±1.0
5.5 − ±0.5 ±5.0
Current
I
OLD
I
OHD
I
CC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5 − − 75 mA V
5.5 − − −75 mA V
5.5 − 8.0 80
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
TA =
−40°C to
+85°C
Unit Conditions
= 0.1 V
OUT
= 0.1 V
OUT
I
= −50 mA
OUT
*VIN = VIL or V
V
OH
I
OUT
−24 mA
= 50 mA
*VIN = VIL or V
mA
mA
V
OL
VI = VCC, GND
V
(OE) = VIL, V
I
VI = VCC, GND
24 mA
VO = VCC, GND
= 1.65 V Max
OLD
= 3.85 V Min
OHD
mA
VIN = VCC or GND
IH
IH
IH
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