ON Semiconductor MC74AC157, MC74ACT157 Technical data

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MC74AC157, MC74ACT157

Quad 2−Input Multiplexer

The MC74AC157/74ACT157 is a high−speed quad 2−input
multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four outputs present the
selected data in the true (noninverted) form.

The MC74AC157/74ACT157 can also be used as a function
generator.

Features

• Outputs Source/Sink 24 mA

• ′ACT157 Has TTL Compatible Inputs

• Pb−Free Packages are Available*

16

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PDIP−16
N SUFFIX
CASE 648

1

V

CC

SI0aI

I

E

0cI1cZcI0dI1dZd

1516 14 13 12 11 10

21 34567

1aZaI0bI1bZb

9

8

GND

Figure 1. Pinout: 16−Lead Packages Conductors

(Top View)

TRUTH TABLE

Inputs Outputs

E S I
H X X X L

L H X L L
L H X H H
L L L X L
L L H X H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

I

0

1

Z

SOIC−16

16

1

16

1

16

1

D SUFFIX

CASE 751B

TSSOP−16
DT SUFFIX

CASE 948F

EIAJ−16
M SUFFIX
CASE 966

PIN NAMES

PIN

I0a−I
I1a−I
E
S
Za−Z

0d
1d

d

FUNCTION

Source 0 Data Inputs
Source 0 Data Inputs
Enable Input
Select Input
Outputs

DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 3 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

January, 2005 − Rev. 6

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.

MC74AC157/D

MC74AC157, MC74ACT157

EI0aI1aI0bI

S

Z

a

Figure 2. Logic Symbol

FUNCTIONAL DESCRIPTION

The MC74AC157/74ACT157 is a quad 2−input
multiplexer. It selects four bits of data from two sources
under the control of a common Select input (S). The Enable
input (E

) is active−LOW. When E is HIGH, all of the outputs
(Z) are forced LOW regardless of all other inputs. The
MC74AC157/74ACT157 is the logic implementation of a
4−pole, 2−position switch where the position of the switch
is determined by the logic levels supplied to the Select input.
The logic equations for the outputs are shown below:

I

0a

I

1a

I

0b

I

1b

I

0c

I0cI1cI0dI

1b

Z

Z

b

c

Z

a

Zb = E•(I
Z

c

Zd = E•(I

Z

d

= E•(I

= E•(I

1d

•S+I0a•S)

1a

•S+I0b•S)

1b

•S+I0c•S)

1c

•S+I0d•S)

1d

A common use of the MC74AC157/74ACT157 is the
moving of data from two groups of registers to four common
output busses. The particular register from which the data
comes is determined by the state of the Select input. A less
obvious use is as a function generator. The
MC74AC157/74ACT157 can generate any four of the
sixteen different functions of two variables with one
variable common. This is useful for implementing gating
functions.

I

1c

I

0d

I

1d

E S

Z

a

NOTE: This diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation delays.

Z

b

Z

c

Figure 3. Logic Diagram

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2

Z

d

MC74AC157, MC74ACT157

r,f

AC Devices exce t Schmitt In uts

In ut Rise and Fall Time (Note 2)

MARKING DIAGRAMS

PDIP−16 SOIC−16 TSSOP−16 EIAJ−16

MC74AC157N

AWLYYWW

AC157

AWLYWW

AC

157

74AC157

ALYW

ALYW

MC74ACT157N

AWLYYWW

ACT157

AWLYWW

ACT

157

74ACT157

ALYW

ALYW

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

MAXIMUM RATINGS

Symbol Parameter Value Unit

V

CC

V

IN

V

OUT

I

IN

I

OUT

I

CC

T

stg

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously . If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.

DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V
DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V
DC Input Current, per Pin ±20 mA
DC Output Sink/Source Current, per Pin ±50 mA
DC VCC or GND Current per Output Pin ±50 mA
Storage Temperature −65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

V

CC

VIN, V

OUT

tr, t

f

tr, t

f

T

J

T

A

I

OH

I

OL

1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2. V

from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

IN

pp

Supply Voltage

′ACT 4.5 5.0 5.5

DC Input Voltage, Output Voltage (Ref. to GND) 0 − V

CC

V

V

VCC @ 3.0 V − 150 −

′AC 2.0 5.0 6.0

Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs

VCC @ 4.5 V − 40 − ns/V
VCC @ 5.5 V − 25 −

Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs

VCC @ 4.5 V − 10 −
VCC @ 5.5 V − 8.0 −

ns/V

Junction Temperature (PDIP) − − 140 °C
Operating Ambient Temperature Range −40 25 85 °C
Output Current − High − − −24 mA
Output Current − Low − − 24 mA

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3

MC74AC157, MC74ACT157

ugee

auoee

ugee

V

auoee

V

au u

A

V

V

GND

†y

a u Quesce

A

V

V

GND

o aga o e ay

Pro agation Delay

Pro agation Delay

Pro agation Delay

Pro agation Delay

Pro agation Delay

DC CHARACTERISTICS

74AC 74AC

V

CC

Symbol Parameter

(V)

TA = +25°C

Typ Guaranteed Limits

V

IH

Minimum High Level
Input Voltage

3.0 1.5 2.1 2.1 V

4.5 2.25 3.15 3.15 V or VCC − 0.1 V

5.5 2.75 3.85 3.85

V

IL

Maximum Low Level
Input Voltage

3.0 1.5 0.9 0.9 V

4.5 2.25 1.35 1.35 V or VCC − 0.1 V

5.5 2.75 1.65 1.65

V

OH

Minimum High Level
Output Voltage

3.0 2.99 2.9 2.9 I

4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

3.0 − 2.56 2.46

4.5 − 3.86 3.76

5.5 − 4.86 4.76 −24 mA

V

OL

Maximum Low Level
Output Voltage

3.0 0.002 0.1 0.1 I

4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

3.0 − 0.36 0.44

4.5 − 0.36 0.44

5.5 − 0.36 0.44 24 mA

I

I

OLD

I

OHD

I

IN

CC

Maximum Input
Leakage Current

†Minimum Dynamic

Output Current

Maximum Quiescent
Supply Current

5.5 − ±0.1 ±1.0 

5.5 − − 75 mA V

5.5 − − −75 mA V

5.5 − 8.0 80 

*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.

NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

TA =

−40°C to
+85°C

Unit Conditions

= 0.1 V

OUT

= 0.1 V

OUT

= −50 A

OUT

*VIN = VIL or V

−12 mA

I

OH

OUT

−24 mA

= 50 A

*VIN = VIL or V

12 mA

I

OL

=

I

OLD
OHD

IN

24 mA

,

CC

= 1.65 V Max

= 3.85 V Min

=

or

CC

IH

IH

AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.

Propagation Delay
S to Z

n

Propagation Delay
S to Z

n

Propagation Delay
E to Z

n

Propagation Delay
En to Z

n

Propagation Delay
In to Z

n

Propagation Delay
In to Z

n

VCC*

(V)

3.3 1.5 7.0 11.5 1.5 13.0

5.0 1.5 5.5 9.0 1.5 10.0

3.3 1.5 6.5 11.0 1.5 12.0

5.0 1.5 5.0 8.5 1.0 9.5

3.3 1.5 7.0 11.5 1.5 13.0

5.0 1.5 5.5 9.0 1.5 10.0

3.3 1.5 6.5 11.0 1.5 12

5.0 1.5 5.5 9.0 1.0 9.5

3.3 1.5 5.0 8.5 1.0 9.0

5.0 1.5 4.0 6.5 1.0 7.0

3.3 1.5 5.0 8.0 1.0 9.0

5.0 1.5 4.0 6.5 1.0 7.0

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4

74AC 74AC

TA = +25°C
C

= 50 pF

L

TA = −40°C

to +85°C

= 50 pF

C

L

Min Typ Max Min Max

Unit

ns 3−6

ns 3−6

ns 3−6

ns 3−6

ns 3−5

ns 3−5

Fig.

No.

MC74AC157, MC74ACT157

ugee

V

auoee

V

ugee

V

I

auoee

V

I

au u

A

V

V

GND

a u Quesce

A

V

V

GND

Pro agation Delay

Pro agation Delay

Pro agation Delay

Pro agation Delay

Pro agation Delay

Pro agation Delay

DC CHARACTERISTICS

V

CC

Symbol Parameter

V

IH

Minimum High Level
Input Voltage

V

IL

Maximum Low Level
Input Voltage

V

OH

Minimum High Level
Output Voltage

(V)

4.5 1.5 2.0 2.0

5.5 1.5 2.0 2.0

4.5 1.5 0.8 0.8

5.5 1.5 0.8 0.8

4.5 4.49 4.4 4.4

5.5 5.49 5.4 5.4

4.5 − 3.86 3.76 V

5.5 − 4.86 4.76

V

OL

Maximum Low Level
Output Voltage

4.5 0.001 0.1 0.1

5.5 0.001 0.1 0.1

4.5 − 0.36 0.44 V

5.5 − 0.36 0.44

I

I
I

I

IN

CCT

OLD

OHD

I

CC

Maximum Input
Leakage Current

5.5 − ±0.1 ±1.0 

Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V
†Minimum Dynamic

Output Current

Maximum Quiescent
Supply Current

5.5 − − 75 mA V

5.5 − − −75 mA V

5.5 − 8.0 80 

*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.

TA = +25°C

Typ Guaranteed Limits

74ACT 74ACT

TA =

−40°C to
+85°C

Unit Conditions

V

= 0.1 V

OUT

or VCC − 0.1 V
V

= 0.1 V

OUT

or VCC − 0.1 V
I

= −50 A

OUT

*VIN = VIL or V

OH

I

OUT

−24 mA

−24 mA

= 50 A

*VIN = VIL or V

OL

I

OLD

OHD

IN

=

24 mA
24 mA

,

CC

= 1.65 V Max

= 3.85 V Min

=

or

CC

IH

IH

AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

74ACT 74ACT

TA = −40°C

to +85°C

= 50 pF

C

L

Unit

Symbol Parameter

t

t

t

t

t

t

PLH

PHL

PLH

PHL

PLH

PHL

Propagation Delay
S to Z

n

Propagation Delay
S to Z

n

Propagation Delay
En to Z

n

Propagation Delay
En to Z

n

Propagation Delay
In to Z

n

Propagation Delay
In to Z

n

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

VCC*

(V)

TA = +25°C
C

= 50 pF

L

Min Typ Max Min Max

5.0 2.0 − 9.0 1.5 10.0 ns 3−6

5.0 2.0 − 9.5 2.0 10.5 ns 3−6

5.0 1.5 − 10 1.5 11.5 ns 3−6

5.0 1.5 − 8.5 1.0 9.0 ns 3−6

5.0 1.5 − 7.0 1.0 8.5 ns 3−5

5.0 1.5 − 7.5 1.0 8.5 ns 3−5

Fig.

No.

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5

MC74AC157, MC74ACT157

†

CAPACITANCE

Symbol Parameter

C

IN

C

PD

Input Capacitance 4.5 pF VCC = 5.0 V
Power Dissipation Capacitance 50 pF VCC = 5.0 V

ORDERING INFORMATION

Device Order Number Package Shipping

MC74AC157N PDIP−16 25 Units / Rail
MC74AC157NG PDIP−16

MC74ACT157N PDIP−16 25 Units / Rail
MC74AC157D SOIC−16 48 Units / Rail
MC74ACT157D SOIC−16 48 Units / Rail
MC74ACT157DG SOIC−16

MC74AC157DR2 SOIC−16 2500 Tape & Reel
MC74AC157DR2G SOIC−16

MC74ACT157DR2 SOIC−16 2500 Tape & Reel
MC74ACT157DR2G SOIC−16

MC74AC157DT TSSOP−16* 96 Units / Rail
MC74ACT157DT TSSOP−16* 96 Units / Rail
MC74AC157DTR2 TSSOP−16* 2500 Tape & Reel
MC74ACT157DTR2 TSSOP−16* 2500 Tape & Reel
MC74AC157M EIAJ−16 50 Units / Rail
MC74ACT157M EIAJ−16 50 Units / Rail
MC74AC157MEL EIAJ−16 2000 Tape & Reel
MC74ACT157MEL EIAJ−16 2000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

Value

Typ

Unit Test Conditions

25 Units / Rail

48 Units / Rail

2500 Tape & Reel

2500 Tape & Reel

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6

MC74AC157, MC74ACT157

PACKAGE DIMENSIONS

PDIP−16

N SUFFIX

CASE 648−08

ISSUE T

−A−

916

B

18

F

C

S

−T−

H

G

D

16 PL

0.25 (0.010) T

K

M

A

SEATING
PLANE

J

M

CASE 751B−05

L

SOIC−16

D SUFFIX

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77

M

G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

M

S

X 45

R



F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7



P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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7

MC74AC157, MC74ACT157

PACKAGE DIMENSIONS

TSSOP−16
DT SUFFIX

CASE 948F−01

ISSUE O

0.10 (0.004)

−T−

SEATING
PLANE

L

U0.15 (0.006) T

PIN 1
IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

16X REFK

0.10 (0.004) V

M

S

U

T

S

K

K1

16

9

J1

B

−U−

1

8

J

N

A

SECTION N−N

0.25 (0.010)

M

−V−
N

F

DETAIL E

C

DETAIL E

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

−W−

L 6.40 BSC 0.252 BSC

M 0 8 0 8



INCHESMILLIMETERS

G

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8

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

E

A

A

1

0.10 (0.004)

MC74AC157, MC74ACT157

PACKAGE DIMENSIONS

EIAJ−16

M SUFFIX

CASE 966−01

ISSUE O

L

E

Q

1

M



L

DETAIL P

VIEW P

c

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A
A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

INCHES

10



10

0





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9

MC74AC157, MC74ACT157

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your
local Sales Representative.

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