Page 1
MC74AC02, MC74ACT02
Quad 2−Input NOR Gate
Features
• Outputs Source/Sink 24 mA
• ′ACT02 Has TTL Compatible Inputs
• Pb−Free Packages are Available
V
CC
1314 12 11 10 9 8
14
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PDIP−14
N SUFFIX
CASE 646
21 34567
GND
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
MAXIMUM RATINGS
Rating Symbol Value Unit
DC Supply Voltage (Referenced to GND) V
DC Input Voltage (Referenced to GND) V
DC Output Voltage (Referenced to GND) V
DC Input Current, per Pin I
DC Output Sink/Source Current, per Pin I
DC VCC or GND Current per Output Pin I
Storage Temperature T
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
CC
in
out
in
out
CC
stg
−0.5 to
+7.0
−0.5 to
VCC +0.5
−0.5 to
VCC +0.5
±20 mA
±50 mA
±50 mA
−65 to
+150
V
V
V
°C
1
14
1
14
1
14
1
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
M SUFFIX
CASE 965
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1 Publication Order Number:
MC74AC02/D
Page 2
MC74AC02, MC74ACT02
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Vin, V
tr, t
f
tr, t
f
T
J
T
A
I
OH
I
OL
out
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND) 0 − V
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
Junction Temperature (PDIP) − − 140 °C
Operating Ambient Temperature Range −40 25 85 °C
Output Current − High − − −24 mA
Output Current − Low − − 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
V
Symbol Parameter
V
IH
Minimum High Level
Input Voltage
V
IL
Maximum Low Level
Input Voltage
V
OH
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
Maximum Input
Leakage Current
I
OLD
I
OHD
I
CC
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
CC
(V)
3.0 1.5 2.1 2.1 V
4.5 2.25 3.15 3.15 V or VCC − 0.1 V
5.5 2.75 3.85 3.85
3.0 1.5 0.9 0.9 V
4.5 2.25 1.35 1.35 V or VCC − 0.1 V
5.5 2.75 1.65 1.65
3.0 2.99 2.9 2.9 I
4.5 4.49 4.4 4.4 V
5.5 5.49 5.4 5.4
3.0 − 2.56 2.46 −12 mA
4.5 − 3.86 3.76 I
5.5 − 4.86 4.76 −24 mA
3.0 0.002 0.1 0.1 I
4.5 0.001 0.1 0.1 V
5.5 0.001 0.1 0.1
3.0 − 0.36 0.44 12 mA
4.5 − 0.36 0.44 I
5.5 − 0.36 0.44 24 mA
5.5 − ±0.1 ±1.0 μA VI = VCC, GND
5.5 − − 75 mA V
5.5 − − −75 mA V
5.5 − 4.0 40 μA VIN = VCC or GND
′AC 2.0 5.0 6.0
′ACT 4.5 5.0 5.5
CC
VCC @ 3.0 V − 150 −
VCC @ 4.5 V − 40 − ns/V
VCC @ 5.5 V − 25 −
VCC @ 4.5 V − 10 −
VCC @ 5.5 V − 8.0 −
74AC 74AC
TA =
TA = +25°C
−40°C to
Unit Conditions
+85°C
Typ Guaranteed Limits
= 0.1 V
OUT
= 0.1 V
OUT
= −50 μA
OUT
*VIN = VIL or V
V
OH
OUT
−24 mA
= 50 μA
*VIN = VIL or V
V
OL
OLD
OHD
24 mA
= 1.65 V Max
= 3.85 V Min
V
V
ns/V
IH
IH
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2
Page 3
MC74AC02, MC74ACT02
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC 74AC
Symbol Parameter
t
PLH
t
PHL
Propagation Delay
Propagation Delay
VCC*
(V)
3.3 1.5 5.0 7.5 1.0 8.0
5.0 1.5 4.0 6.0 1.0 6.5
3.3 1.5 5.0 7.5 1.0 8.0
5.0 1.5 4.5 6.5 1.0 7.0
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
DC CHARACTERISTICS
V
CC
Symbol Parameter
V
IH
Minimum High Level
Input Voltage
V
IL
Maximum Low Level
Input Voltage
V
OH
Minimum High Level
Output Voltage
V
OL
Maximum Low Level
Output Voltage
I
IN
Maximum Input
Leakage Current
ΔI
I
OLD
I
OHD
I
CC
CCT
Additional Max. ICC/Input 5.5 0.6 − 1.5 mA VI = VCC − 2.1 V
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
TA = +25°C
(V)
Typ Guaranteed Limits
4.5 1.5 2.0 2.0
5.5 1.5 2.0 2.0 or VCC − 0.1 V
4.5 1.5 0.8 0.8
5.5 1.5 0.8 0.8 or VCC − 0.1 V
4.5 4.49 4.4 4.4
5.5 5.49 5.4 5.4
4.5 − 3.86 3.76 V
5.5 − 4.86 4.76 −24 mA
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
4.5 − 0.36 0.44 V
5.5 − 0.36 0.44 24 mA
5.5 − ±0.1 ±1.0 μA VI = VCC, GND
5.5 − − 75 mA V
5.5 − − −75 mA V
5.5 − 4.0 40 μA VIN = VCC or GND
TA = +25°C
CL = 50 pF
Min Typ Max Min Max
74ACT 74ACT
TA =
−40°C to
+85°C
TA = −40°C
to +85°C
Unit
CL = 50 pF
ns 3−5
ns 3−5
Unit Conditions
V
= 0.1 V
V
I
OUT
OUT
OUT
= 0.1 V
= −50 μA
V
V
V
*VIN = VIL or V
I
OH
I
V
OUT
−24 mA
= 50 μA
*VIN = VIL or V
I
OL
= 1.65 V Max
OLD
= 3.85 V Min
OHD
24 mA
Fig.
No.
IH
IH
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3
Page 4
MC74AC02, MC74ACT02
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT 74ACT
TA = −40°C
to +85°C
CL = 50 pF
Unit
Symbol Parameter
t
PLH
t
PHL
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
Propagation Delay 5.0 1.5 − 8.5 1.0 9.0 ns 3−6
Propagation Delay 5.0 1.5 − 9.5 1.0 10 ns 3−6
CAPACITANCE
Symbol Parameter
C
IN
C
PD
Input Capacitance 4.5 pF VCC = 5.0 V
Power Dissipation Capacitance 30 pF VCC = 5.0 V
VCC*
(V)
TA = +25°C
CL = 50 pF
Min Typ Max Min Max
Value
Typ
Unit Test Conditions
Fig.
No.
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4
Page 5
DEVICE ORDERING INFORMATION
MC74AC02, MC74ACT02
Device Package Shipping
MC74AC02N PDIP−14
MC74AC02NG PDIP−14
MC74ACT02N PDIP−14
MC74ACT02NG PDIP−14
MC74AC02D SOIC−14
MC74AC02DG SOIC−14
MC74AC02DR2 SOIC−14
MC74AC02DR2G SOIC−14
MC74ACT02D SOIC−14
MC74ACT02DG SOIC−14
MC74ACT02DR2 SOIC−14
MC74ACT02DR2G SOIC−14
MC74AC02DT TSSOP−14* 96 Units/Rail
MC74AC02DTR2 TSSOP−14*
MC74AC02DTR2G TSSOP−14*
MC74ACT02DT TSSOP−14* 96 Units/Rail
MC74ACT02DTR2 TSSOP−14*
MC74ACT02DTR2G TSSOP−14*
MC74AC02M SOEIAJ−14 50 Units/Rail
MC74AC02MEL SOEIAJ−14
MC74AC02MELG SOEIAJ−14
MC74ACT02MEL SOEIAJ−14
MC74ACT02MELG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
(Pb−Free)
25 Units/Rail
(Pb−Free)
55 Units/Rail
(Pb−Free)
2500/Tape & Reel
(Pb−Free)
55 Units/Rail
(Pb−Free)
2500/Tape & Reel
(Pb−Free)
2500/Tape & Reel
2500/Tape & Reel
(Pb−Free)
2000/Tape & Reel
SOEIAJ−14
(Pb−Free)
†
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5
Page 6
MC74AC02, MC74ACT02
MARKING DIAGRAMS
PDIP−14 SOIC−14 TSSOP−14
14
MC74AC02N
AWLYYWWG
1
14
MC74ACT02N
AWLYYWWG
1
14
AC02
AWLYWWG
1
14
ACT02
AWLYWWG
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
14
14
1
1
AC
02
ALYWG
G
ACT
02
ALYWG
G
SOEIAJ−14
14
74AC02
ALYWG
1
14
74ACT02
ALYWG
1
http://onsemi.com
6
Page 7
−T−
SEATING
PLANE
14 8
17
N
HG
MC74AC02, MC74ACT02
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B
A
F
L
C
D
14 PL
0.13 (0.005)
K
J
M
M
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
0.290 0.310 7.37 7.87
M −−− 10 −−− 10
N 0.015 0.039 0.38 1.01
MILLIMETERSINCHES
__
http://onsemi.com
7
Page 8
−T−
SEATING
PLANE
MC74AC02, MC74ACT02
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−A−
14
1
8
−B−
7
P 7 PL
0.25 (0.010) B
M
M
G
F
J
D 14 PL
0.25 (0.010) A
M
T
R X 45
C
K
S
B
S
_
M
SOLDERING FOOTPRINT*
7X
7.04
1
14X
0.58
14X
1.52
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
__ __
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
Page 9
MC74AC02, MC74ACT02
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
0.10 (0.004)
−T−
SEATING
PLANE
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
−V−
B
N
−U−
F
7
DETAIL E
K
K1
J
J1
SECTION N−N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
−W−
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
INCHESMILLIMETERS
SOLDERING FOOTPRINT*
7.06
1
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
0.65
PITCH
Page 10
14 8
1
Z
D
e
b
0.13 (0.005)
M
E
7
A
0.10 (0.004)
H
A
1
MC74AC02, MC74ACT02
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
L
E
E
VIEW P
_
M
L
DETAIL P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q
1
c
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.10 0.20 0.004 0.008
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
0.50
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
−−− 1.42 −−− 0.056
Z
INCHES
10
_
10
0
_
_
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MC74AC02/D
10
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