MC3479
Stepper Motor Driver
The MC3479 is designed to drive a two−phase stepper motor in the
bipolar mode. The circuit consists of four input sections, a logic
decoding/sequencing section, two driver−stages for the motor coils,
and an output to indicate the Phase A
• Single Supply Operation: 7.2 to 16.5 V
• 350 mA/Coil Drive Capability
• Clamp Diodes Provided for Back−EMF Suppression
• Selectable CW/CCW and Full/Half Step Operation
• Selectable High/Low Output Impedance (Half Step Mode)
• TTL/CMOS Compatible Inputs
• Input Hysteresis: 400 mV Minimum
• Phase Logic Can Be Initialized to Phase A
• Phase A Output Drive State Indication (Open−Collector)
Clk
Clock
drive state.
V
M
Driver
L1
PLASTIC PACKAGE
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STEPPER MOTOR
DRIVER
PDIP
P SUFFIX
CASE 648C
MARKING
DIAGRAM
MC3479P
AWLYYWW
CW
Full
Step
/CCW
/Half
OIC
CW/CCW
F
/H Step
OIC
Logic
Driver
GndBias/SetPhase A
Figure 1. Representative Block Diagram
ORDERING INFORMATION
Operating
Device
MC3479P TA = 0° to +70°C PDIP 25 Units / Rail
MC3479P TA = 0° to +70°C PDIP 2000 Units / Box
Temperature Range
Package Shipping
L2
V
D
L3
L4
Gnd
Bias
/CCW
CW
Full/Half Step
OIC
MC3479P = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN CONNECTIONS
16
15
14
13
12
11
10
9
V
M
L3
L4
Gnd
Phase A
CW/CCW
l/Half
Ful
Step
/Set
OIC
1
V
D
2
L2
3
L1
4
5
6
Clk
7
8
(Top View)
INPUT TRUTH TABLE
Input Low Input High
CW CCW
Full Step Half Step
Hi Z Low Z
Positive Edge TriggeredClk
Semiconductor Components Industries, LLC, 2003
November, 2003 − Rev. 5
1 Publication Order Number:
MC3479/D
MC3479
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage V
Clamp Diode Cathode Voltage (Pin 1) V
Driver Output Voltage V
Drive Output Current/Coil I
Input Voltage (Logic Controls) V
Bias/Set Current I
Phase A Output Voltage V
Phase A Sink Current I
Junction Temperature T
Storage Temperature Range T
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Min Max Unit
Supply Voltage V
Clamp Diode Cathode Voltage V
Driver Output Current (Per Coil) (Note 1) I
Input Voltage (Logic Controls) V
Bias/Set Current (Outputs Active) I
Phase A Output Voltage V
Phase A Sink Current I
Operating Ambient Temperature T
1. See section on Power Dissipation in Application Information.
OD
OD
BS
OA
OA
stg
OD
BS
OA
OA
M
D
+ 18 Vdc
VM + 5.0 Vdc
VM + 6.0 Vdc
± 500 mA
in
− 0.5 to + 7.0 Vdc
− 10 mA
+ 18 Vdc
20 mA
J
+ 150 °C
− 65 to + 150 °C
+ 7.2 + 16.5 Vdc
M
D
V
M
− 350 mA
in
0 + 5.5 Vdc
−300 − 75 A
− V
0 8.0 mA
A
0 + 70 °C
V
+ 4.5 Vdc
M
M
Vdc
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2
MC3479
Out ut High Voltage (I
BS
300 A)
I
OD
350 mA
2, 3
V
OHD
V
M
2.0
Vdc
DC ELECTRICAL CHARACTERISTICS (Specifications apply over the recommended supply voltage and temperature range,
(Notes 2, 3) unless otherwise noted.)
Characteristic
INPUT LOGIC LEVELS
Threshold Voltage (Low−to−High)
Threshold Voltage (High−to−Low)
Hysteresis V
Current: (VI = 0.4 V)
(VI = 5.5 V)
(V
= 2.7 V)
I
DRIVER OUTPUT LEVELS
Output High Voltage (I
= − 300 A) IOD = − 350 mA 2, 3, V
BS
IOD = − 0.1 mA
Output Low Voltage (IBS = − 300 A, IOD = 350 mA) V
Differential Mode Output Voltage Difference (Note 4)
(I
= − 300 A, IOD = 350 mA)
BS
Output Leakage, Hi Z State
(0 VOD VM, IBS = − 5.0 A)
(0 V
VM, IBS = − 300 A, F/H = 2.0 V, OIC = 0.8 V)
OD
CLAMP DIODES
Forward Voltage
= 350 mA)
(I
D
Leakage Current (Per Diode)
(Pin 1 = 21 V; Outputs = 0 V; IBS = 0 A)
PHASE A OUTPUT
Output Low Voltage
(I
= 8.0 mA)
OA
Off State Leakage Current
(V
= 16.5 V)
OHA
POWER SUPPLY
Power Supply Current
= 0 A, IBS = − 300 A)
(I
(L1 = V
(L1 = V
(L1 = V
OHD
OHD
, L2 = V
OHD
, L2 = V
OLD
, L2 = V
OLD
OD
, L3 = V
, L3 = Hi Z, L4 = Hi Z)
OLD
, L3 = V
OHD
OHD
, L4 = V
, L4 = V
OLD
OHD
)
)
BIAS/SET CURRENT
To Set Phase A 6 I
2. Algebraic convention rather than absolute values is used to designate limit values.
3. Current into a pin is designated as positive. Current out of a pin is designated as negative.
4. DVOD = V
OD
= V
5. CV
OD1,2
OHD1
− V
− V
OD3,4
OHD2
where:V
or V
OHD3
OD1,2
− V
= (V
OHD4
OHD1
.
− V
OLD2
) or (V
OHD2
− V
OLD1
Pins Symbol Min Typ Max Unit
7, 8,
9, 10
14, 15
14, 15 DV
,
V
TLH
V
THL
HYS
I
IL
OHDVM
OLD
OD
CV
OD
− − 2.0 Vdc
0.8 − − Vdc
0.4 − − Vdc
−100
−
−
−2.0 − − Vdc
V
−1.2 − −
M
−
−
+100
−
+20
− − 0.8 Vdc
−
−
−−0.15
0.15
14, 15
1, 2, 3,
14, 15
11
V
I
I
OZ1
I
OZ2
V
I
DR
OLA
OHA
DF
−100
−100
−−+100
+100
− 2.5 3.0 Vdc
− − 100 A
− − 0.4 Vdc
− − 100 A
16
), and V
OD3,4
I
I
I
= (V
MW
MZ
MN
BS
OHD3
−
−
−
−
70
−
40
−
75
− 5.0 − − A
− V
OLD4
) or (V
OHD4
− V
−
A
Vdc
A
mA
).
OLD3
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance, Junction−to−Ambient (No Heatsink) R
Characteristic Symbol Min Typ Max Unit
JA
− 45 − °C/W
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3
MC3479
AC SWITCHING CHARACTERISTICS (T
Characteristic
= + 25°C, VM = 12 V) (See Figures 2, 3, 4)
A
Pins Symbol Min Typ Max Unit
Clock Frequency 7 f
Clock Pulse Width (High) 7 PW
Clock Pulse Width (Low) 7 PW
Bias/Set Pulse Width 6 PW
Setup Time (CW/CCW and F/HS) 10−7
9−7
Hold Time (CW/CCW and F/HS) 10−7
9−7
Propagation Delay (Clk−to−Driver Output) t
Propagation Delay (Bias/Set−to−Driver Output) t
Propagation Delay (Clk−to−Phase A Low) 7−11 t
Propagation Delay (Clk−to−Phase A High) 7−11 t
6. Algebraic convention rather than absolute values is used to designate limit values.
7. Current into a pin is designated as positive. Current out of a pin is designated as negative.
CK
CKH
CKL
t
su
t
h
PCD
PBSD
PHLA
PLHA
0 − 50 kHz
10 − − s
10 − − s
10 − − s
BS
5.0 − − s
10 − − s
− 8.0 − s
− 1.0 − s
− 12 − s
− 5.0 − s
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4
CW
Bias
F
/ CCW
/Set
Clk
OIC
/ HS
56 k
+ 12 V
V
M
16
2
6
7
8
9
10
41213
3
MC3479P
14
15
5
0.1 F
L2
L1
L4
L3
11
4.0 k
1.0 k
1.0 k
1.0 k
1.0 k
1.0 k
1.0 k
+ 12 V
Phase A
MC3479
Bias/Set
Input
L1 − L4
Outputs
0
PW
V
M
VM − 1.0 VM − 1.0
Note: tr, t
input signals are 25 ns.
BS
t
PBSD
(High Impedance)
(10% to 90%) for
f
t
PBSD
Figure 2. AC Test Circuit
Figure 3. Bias/Set Timing (Refer to Figure 2)
PIN FUNCTION DESCRIPTION
Pin No.
20−Pin 16−Pin
20 16 Power Supply V
4, 5, 6, 7,
14, 15, 16, 17
4, 5,
12, 13
1 1 Clamp Diode Voltage V
2, 3,
18, 19
2, 3,
14, 15
8 6 Bias/Set B/S This pin is typically 0.7 volts below VM. The current out of this pin (through
9 7 Clock Clk The positive edge of the clock input switches the outputs to the next
11 9 Full/Half Step F/HS When low (Logic “0”), each clock input pulse will cause the motor to rotate
12 10 Clockwise/
10 8 Output Impedance
13 11 Phase A Ph A This open−collector output indicates (when low) that the driver outputs are
Function Symbol Description
Power supply pin for both the logic circuit and the motor coil current.
M
Voltage range is + 7.2 to + 16.5 V.
Ground GND Ground pins for the logic circuit and the motor coil current. The physical
configuration of the pins aids in dissipating heat from within the IC
package.
This pin is used to protect the outputs where large voltage spikes may
D
occur as the motor coils are switched. Typically a diode is connected
between this pin and Pin 16. See Figure 12.
Driver Outputs L1, L2
L3, L4
High current outputs for the motor coils. L1 and L2 are connected to one
coil, and L3 and L4 to the other coil.
a resistor to ground) determines the maximum output sink current. If the pin
is opened (I
while the internal logic presets to a Phase A
< 5.0 A) the outputs assume a high impedance condition,
BS
condition.
position. This input has no effect if Pin 6 is open.
one full step. When high, each clock pulse will cause the motor to rotate
one−half step. See Figure 7 for sequence.
Counterclockwise
CW/
CCW
This input allows reversing the rotation of the motor. See Figure 7 for
sequence.
OIC This input is relevant only in the half step mode (Pin 9 > 2.0 V). When low
Control
(Logic “0”), the two driver outputs of the non−energized coil will be in a high
impedance condition. When high the same driver outputs will be at a low
impedance referenced to V
in the Phase A condition (L1 = L3 = V
. See Figure 7.
M
OHD
, L2 = L4 = V
OLD
).
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5
MC3479
APPLICATION INFORMATION
General
The MC3479 integrated circuit is designed to drive a
stepper positioning motor in applications such as disk drives
and robotics. The outputs can provide up to 350 mA to each
of two coils of a two−phase motor. The outputs change state
with each low−to−high transition of the clock input, with the
new output state depending on the previous state, as well as
the input conditions at the logic controls.
PW
CLKL
su
1.5 V
1.5 V
Figure 4. Clock Timing
(Refer to Figure 2)
/HS,
F
CW
Inputs
Clk
L1 − L4
Outputs
/CCW
Phase A
Output
3.0 V
PW
CLKH
3.0 V
t
1.5 V
PCD
6.0 V
0
0
Outputs
The outputs (L1−L4) are high current outputs (see
Figure 5), which when connected to a two−phase motor,
provide two full−bridge configurations (L3 and L4 are not
shown in Figure 5). The polarities applied to the motor coils
depend on which transistor (Q
or QL) of each output is on,
H
which in turn depends on the inputs and the decoding
circuitry.
tht
t
PHLA
t
PLHA
Note: tr, tf (10% to 90%) for
input signals are 10 ns.
I′
BS
B/S
I
BS
R
B
Current
Drivers
and
Logic
To L3, L4
Transistors
CW
Figure 5. Output Stages
The maximum sink current available at the outputs is a
function of the resistor connected between Pin 6 and ground
(see section on Bias
/Set operation). Whenever the outputs
V
V
Parasitic
Diodes
OIC
D
Q
H
L2
Q
L
M
/ CCW
Q
H
Q
L
Logic Decoding
/HS
Motor Coil
L1
Circuit
ClkF
Inputs
are to be in a high impedance state, both transistors (Q
QL of Figure 5) of each output are off.
H
and
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6
MC3479
V
D
This pin allows for provision of a current path for the
motor coil current during switching, in order to suppress
back−EMF voltage spikes. V
is normally connected to V
D
(Pin 16) through a diode (zener or regular), a resistor, or
directly. The peaks instantaneous voltage at the outputs must
not exceed VM by more than 6.0 V. The voltage drop across
the internal clamping diodes must be included in this portion
of the design (see Figure 6). Note the parasitic diodes
(Figure 5) across each Q
of each output provide for a
L
complete circuit path for the switched current.
3.0
2.0
F
V (V)
1.0
0
ID (mA)
Figure 6. Clamp Diode Characteristics
Full/Half Step
300100 2000
When this input is at a Logic “0” (< 0.8 V), the outputs
change a full step with each clock cycle, with the sequence
direction depending on the CW/CCW input. There are four
steps (Phase A, B, C, D) for each complete cycle of the
sequencing logic. Current flows through both motor coils
during each step, as shown in Figure 7.
When taken to a Logic “1” (>2.0 V), the outputs change
a half step with each clock cycle, with the sequence direction
depending on the CW
M
H) result for each complete cycle of the sequencing logic.
/CCW input. Eight steps (Phase A to
Phase A, C, E and G correspond (in polarity) to Phase A, B,
C
, and D, respectively, of the full step sequence. Phase B, D,
F and H provide current to one motor coil, while
de−energizing the other coil. The condition of the outputs of
the de−energized coil depends on the OIC input, see Figure 7
timing diagram.
OIC
The output impedance control input determines the output
impedance to the de−energized coil when operating in the
half−step mode. When the outputs are in Phase B, D, F or H
(Figure 7) and this input is at a Logic “0” (<0.8 V), the two
outputs to the de−energized coil are in a high impedance
condition − Q
and QH of both outputs (Figure 5) are off.
L
When this input is at a Logic “1” (>2.0 V), a low impedance
output is provided to the de−energized coil as both outputs
have Q
on (QL off). To complete the low impedance path
H
requires connecting VD to VM as described elsewhere in this
data sheet.
Bias/Set
This pin can be used for three functions: a) determining
the maximum output sink current; b) setting the internal
logic to a known state; and c) reducing power consumption.
a) The maximum output sink current is determined by the
base drive current supplied to the lower transistors (Q
Figure 5) of each output, which in turn, is a function of I
L
s of
BS.
The appropriate value of IBS can be approximated using
Figure 11.
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7
Bias
CW
Phase A
Output
MC3479
Clk
/Set
/CCW
Phase A A
L1
L2
L3
L4
DBC
A
(a) Full Step Mode
F
OIC
/HS
BCDBCB
= High Impedance
= Logic 0"
= Don′t Care
A
L1
L2
L3
L4
(b) Half Step Mode
F
EC
Phase A
Output
BD
L1
L2
L3
L4
(c) Half Step Mode
Figure 7. Output Sequence
The value of RB (between this pin and ground) is then
determined by:
VM 0.7 V
R
B
I
BS
b) When this pin is opened (raised to VM) such that IBS is
<5.0 A, t he internal logic i s set to t he Phase A
condition, and
the four driver outputs a re p ut i nto a h igh i mpedance s tate. The
Phase A output (Pin 1 1) g oes a ctive ( low), and i nput s ignals a t
the controls are ignored d uring t his t ime. U pon r e−establishing
IBS, the driver outputs become active, and will be in the Phase
A position (L1 = L3 = V
, L2 = L4 = V
OHD
). The circuit
OLD
will then respond to the inputs at the controls.
The Set function (opening this pin) can be used as a
power−up reset while supply voltages are settling. A CMOS
logic gate (powered by VM) can be used to control this pin
as shown in Figure 12.
c) Whenever the motor is not being stepped, power
dissipation in the IC and in the motor may be lowered by
reducing I
, so as to reduce the output (motor) current.
BS
Setting IBS to 75 A will reduce the motor current, but will
not reset the internal logic as described above. See Figure 13
for a suggested circuit.
A
/CCW = Logic 0"
CW
F/HS = Logic 1", OIC = Logic 0"
GH B
= High Impedance
AA
CDBHGDBC EF
CD
Power Dissipation
The power dissipated by the MC3479 must be such that
the junction temperature (TJ) does not exceed 150°C. The
power dissipated can be expressed as:
P = (VM IM) + (2 IOD) [(VM − V
where VM = Supply voltage;
= Supply current other than IOD;
I
M
I
= Output current to each motor coil;
OD
V
OHD
V
OLD
The power supply current (IM) is obtained from Figure 8.
After the power dissipation is calculated, the junction
temperature can be calculated using:
= (P R
T
J
where R
) + T
JA
JA
A
= Junction−to−ambient thermal resistance
(52°C/W for the DIP, 72°C/W for the FN Package);
TA = Ambient Temperature.
CW
F/HS
OIC
OHD
= Logic 1"
= Logic 1"
) + V
OLD
= Logic 0"
/CCW
= Driver output high voltage;
= Driver output low voltage.
]
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8
MC3479
0.8
70
60
50
40
(mA)
M
I
30
20
10
0
IOD = 0
50
150 200 250 300 350100
I
(A)
BS
Figure 8. Power Supply Current
For example, assume an application where VM = 12 V, the
motor requires 200 mA/coil, operating at room temperature
with no heatsink on the IC. From Figure 11, I
BS
is
determined to be 95 A.
RB is calculated:
RB = (12 − 0.7) V/95 A
RB = 118.9 k
From Figure 8, IM (max) is determined to be 22 mA. From
Figure 9, V
is 0.46 V, and from Figure 10, (VM − V
OLD
OHD
is 1.4 volts.
P = (12 0.022) + (2 0.2) (1.4 + 0.46)
P = 1.01 W
0.6
(VOLTS)
0.4
OLD
V
0.2
0
0 100 200 300
IOD (mA)
Figure 9. Maximum Saturation V oltage −
Driver Output Low
TJ = (1.01 W 52°C/W) + 25°C
TJ = 77.5°C
This temperature is well below the maximum limit. If the
calculated TJ had been higher than 150°C, a heatsink such
as the Staver Co. V−7 Series, Aavid #5802, or Thermalloy
#6012 could be used to reduce R
. In extreme cases,
JA
forced air cooling should be considered.
The above calculation, and R
, assumes that a ground
JA
plane is provided under the MC3479 (either or both sides of
)
the PC board) to aid in the heat dissipation. Single nominal
width traces leading from the four ground pins should be
avoided as this will increase T
, as well as provide
J
potentially disruptive ground noise and I
switching the motor current.
drops when
R
2.0
1.5
] (VOLTS)
1.0
OHD
− V
M
0.5
[V
0
0 100 200 300
(mA)
I
OD
Figure 10. Maximum Saturation Voltage −
Driver Output High
140.00
120.00
100.00
80.00
(A)
60.00
BS
I
40.00
20.00
0.00
0.00 50.00 100.00 150.00 200.00 250.00 300.00
IOD (mA)
Figure 11. Bias/Set Current − Output Drive Current
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9
+V
MC3479
+V
1N5221A (3.0 V)
Digital Inputs
Full
/Half Step
Phase A
Clock
/CCW
CW
2.0 k
Typ
V
M
11
16
7
MC3479
10
9
OIC
8614
Gnd
Set
Normal
Operation
MC14049UB
or equivalent
Figure 12. Typical Applications Circuit
V
D
L1
1
3
Motor
L2
2
L3
15
L4
131245
Bias
/Set
R
B
Normal
Operation
MC3479
6
Bias
/Set
R
B
Reduced
Power
MC14049UB
or equivalent
− Suggested value for RB1 (VM = 12 V) is 150 k.
− RB calculation (see text) must take into account
the current through RB1.
Figure 13. Power Reduction
R
B1
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10
MC3479
PACKAGE DIMENSIONS
PDIP
P SUFFIX
PLASTIC PACKAGE
CASE 648C−04
ISSUE D
A
16 9
18
A
F
E
G
B
B
N
C
K
D
16X
0.005 (0.13) T
M
T
A
L
SEATING
PLANE
M
B
M
J
16X
0.005 (0.13) T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
DIM MIN MAX MIN MAX
A 0.744 0.783 18.90 19.90
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
E 0.050 BSC 1.27 BSC
F 0.040 0.70 1.02 1.78
G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.040 0.39 1.01
MILLIMETERSINCHES
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11
MC3479
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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local Sales Representative.
MC3479/D
12
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