查询MC33201DR2供应商
MC33201, MC33202,
MC33204, NCV33202,
NCV33204
Low Voltage, Rail−to−Rail
Operational Amplifiers
The MC33201/2/4 family of operational amplifiers provide
rail−to−rail operation on both the input and output. The inputs can be
driven as high as 200 mV beyond the supply rails without phase
reversal on the outputs, and the output can swing within 50 mV of each
rail. This rail−to−rail operation enables the user to make full use of the
supply voltage range available. It is designed to work at very low
supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V
and ground. Output current boosting techniques provide a high output
current capability while keeping the drain current of the amplifier to a
minimum. Also, the combination of low noise and distortion with a
high slew rate and drive capability make this an ideal amplifier for
audio applications.
• Low Voltage, Single Supply Operation
(+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Over−driven Input Signals
• High Output Current (I
• Low Supply Current (I
• 600 Output Drive Capability
• Extended Operating Temperature Ranges
(−40° to +105°C and −55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
• Pb−Free Packages are Available
= 80 mA, Typ)
SC
= 0.9 mA, Typ)
D
14
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8
1
8
1
8
1
1
14
1
PDIP−8
P, VP SUFFIX
CASE 626
SOIC−8
D, VD SUFFIX
CASE 751
Micro8
DM SUFFIX
CASE 846A
PDIP−14
P, VP SUFFIX
CASE 646
SOIC−14
D, VD SUFFIX
CASE 751A
Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 12
14
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
1 Publication Order Number:
TSSOP−14
DTB SUFFIX
CASE 948G
MC33201/D
MC33201, MC33202, MC33204, NCV33202, NCV33204
PIN CONNECTIONS
NC
Inputs
V
EE
All Case Styles
Output 1
Inputs 1
V
EE
MC33201
All Case Styles
1
2
3
4
(Top View)
MC33202
1
2
3
4
8
7
1
6
2
5
(Top View)
8
7
6
5
NC
V
CC
Output
NC
V
CC
Output 2
Inputs 2
Output 1
Inputs 1
V
Inputs 2
Output 2
MC33204
All Case Styles
1
2
3
4
CC
7
(Top View)
1
2
Output 4
14
13
4
3
12
11
105
96
8
Inputs 4
V
EE
Inputs 3
Output 3
V
CC
V
CC
V
CC
V
in−
V
in+
V
EE
V
out
V
CC
V
EE
This device contains 70 active transistors (each amplifier).
Figure 1. Circuit Schematic
(Each Amplifier)
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2
MC33201, MC33202, MC33204, NCV33202, NCV33204
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (VCC to VEE) V
Input Differential Voltage Range V
Common Mode Input Voltage Range (Note 2) V
Output Short Circuit Duration t
Maximum Junction Temperature T
Storage Temperature T
Maximum Power Dissipation P
IDR
CM
s
stg
S
+13 V
Note 1 V
VCC + 0.5 V to
− 0.5 V
V
EE
V
Note 3 sec
J
+150 °C
− 65 to +150 °C
D
Note 3 mW
DC ELECTRICAL CHARACTERISTICS (T
= 25°C)
A
Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Unit
Input Offset Voltage
V
IO (max)
MC33201
MC33202, NCV33202
MC33204
± 8.0
±10
±12
± 8.0
±10
±12
± 6.0
± 8.0
±10
mV
Output Voltage Swing
V
(RL = 10 k)
OH
(RL = 10 k)
V
OL
Power Supply Current
per Amplifier (I
)
D
1.9
0.10
3.15
0.15
4.85
0.15
1.125 1.125 1.125
V
V
min
max
mA
Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND.
DC ELECTRICAL CHARACTERISTICS (V
= + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
CC
Characteristic Figure Symbol Min Typ Max Unit
Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V)
MC33201: T
MC33201: T
MC33201V: T
MC33202: T
MC33202: T
MC33202V: T
NCV33202V: T
MC33204: T
MC33204: T
MC33204V: T
= + 25°C
A
= − 40° to +105°C
A
= − 55° to +125°C
A
= + 25°C
A
= − 40° to +105°C
A
= − 55° to +125°C
A
= − 55° to +125°C (Note 4)
A
= + 25°C
A
= − 40° to +105°C
A
= − 55° to +125°C
A
Input Offset Voltage Temperature Coefficient (RS = 50 )
= − 40° to +105°C
T
A
T
= − 55° to +125°C
A
Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
T
= + 25°C
A
= − 40° to +105°C
T
A
T
= − 55° to +125°C
A
Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V)
= + 25°C
T
A
T
= − 40° to +105°C
A
= − 55° to +125°C
T
A
Common Mode Input Voltage Range − V
3 VIO
4 VIO/T
5, 6 IIB
− IIO
ICR
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6.0
9.0
13
8.0
11
14
14
10
13
17
V/°C
mV
−
−
2.0
2.0
−
−
nA
−
−
−
80
100
−
200
250
500
nA
−
−
−
V
EE
5.0
10
−
− V
50
100
200
CC
V
1. The differential input voltage of each amplifier is limited by two internal parallel back−to−back diodes. For additional differential input voltage
range, use current limiting resistors in series with the input pins.
2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage
on either input must not exceed either supply rail by more than 500 mV.
3. Power dissipation must be considered to ensure maximum junction temperature (T
4.
NCV33202 and NCV33204 are qualified for automotive use.
) is not exceeded. (See Figure 2)
J
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3
MC33201, MC33202, MC33204, NCV33202, NCV33204
DC ELECTRICAL CHARACTERISTICS (cont.) (V
Characteristic
Large Signal Voltage Gain (VCC = + 5.0 V, VEE = − 5.0 V)
R
= 10 k
L
= 600
R
L
Output Voltage Swing (VID = ± 0.2 V)
R
= 10 k
L
= 10 k
R
L
R
= 600
L
= 600
R
L
= + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
CC
Figure Symbol Min Typ Max Unit
7 A
VOL
50
25
300
250
8, 9, 10
V
OH
V
OL
V
OH
V
OL
4.85
−
4.75
−
4.95
0.05
4.85
0.15
−
−
−
0.15
−
0.25
Common Mode Rejection (Vin = 0 V to 5.0 V) 11 CMR 60 90 − dB
Power Supply Rejection Ratio
V
= 5.0 V/GND to 3.0 V/GND
CC/VEE
Output Short Circuit Current (Source and Sink) 13, 14 I
Power Supply Current per Amplifier (VO = 0 V)
= − 40° to +105°C
T
A
T
= − 55° to +125°C
A
AC ELECTRICAL CHARACTERISTICS (V
= + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.)
CC
12 PSRR
SC
15 I
D
500 25 −
50 80 − mA
−
−
0.9
0.9
1.125
1.125
Characteristic Figure Symbol Min Typ Max Unit
Slew Rate
= ± 2.5 V, VO = − 2.0 V to + 2.0 V, RL = 2.0 k, AV = +1.0)
(V
S
16, 26 SR
0.5 1.0 −
Gain Bandwidth Product (f = 100 kHz) 17 GBW − 2.2 − MHz
Gain Margin (RL = 600 , CL = 0 pF) 20, 21, 22 A
Phase Margin (RL = 600 , CL = 0 pF) 20, 21, 22
M
M
− 12 − dB
− 65 − Deg
Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) 23 CS − 90 − dB
Power Bandwidth (VO = 4.0 Vpp, RL = 600 , THD ≤ 1 %) BW
Total Harmonic Distortion (RL = 600 , VO = 1.0 Vpp, AV = 1.0)
24 THD
f = 1.0 kHz
f = 10 kHz
Open Loop Output Impedance
(V
= 0 V, f = 2.0 MHz, AV = 10)
O
ZO
Differential Input Resistance (VCM = 0 V) R
Differential Input Capacitance (VCM = 0 V) C
Equivalent Input Noise Voltage (RS = 100 )
25 e
f = 10 Hz
f = 1.0 kHz
Equivalent Input Noise Current
25 i
f = 10 Hz
f = 1.0 kHz
P
in
in
n
n
− 28 − kHz
−
0.002
−
0.008
−
−
− 100 −
− 200 − k
− 8.0 − pF
−
−
−
−
25
20
0.8
0.2
−
−
−
−
kV/V
V
V/V
mA
V/s
%
nV/
Hz
pA/
Hz
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MC33201, MC33202, MC33204, NCV33202, NCV33204
W
2500
8 and 14 Pin DIP Pkg
2000
1500
TSSOP−14 Pkg
SO−14 Pkg
1000
500
, MAXIMUM POWER DISSIPATION (m
0
D(max)
P
SOIC−8
Pkg
T
, AMBIENT TEMPERATURE (°C)
A
Figure 2. Maximum Power Dissipation
40
35
30
25
20
15
10
PERCENTAGE OF AMPLIFIERS (%)
5.0
0
−10 0 4.0 8.0 10−55 −40 −25 0 25 50 85 125
Figure 3. Input Offset Voltage Distribution
360 amplifiers tested from
3 (MC33204) wafer lots
V
VEE = Gnd
T
DIP Package
−2.0 2.0 6.0−6.0−8.0 −4.0
V
, INPUT OFFSET VOLTAGE (mV)
IO
= +5.0 V
CC
= 25°C
A
versus Temperature
50
360 amplifiers tested from
40
3 (MC33204) wafer lots
VCC = +5.0 V
VEE = Gnd
T
= 25°C
30
A
DIP Package
200
160
120
VCC = +5.0 V
VEE = Gnd
VCM = 0 V to 0.5 V
20
10
0
−50 0 20 40 50−10 10 30−30−40 −20
PERCENTAGE OF AMPLIFIERS (%)
TC
, INPUT OFFSET VOLTAGE
V
IO
Temperature Coefficient Distribution
150
TEMPERATURE COEFFICIENT (V/°C)
Figure 4. Input Offset Voltage
80
, INPUT BIAS CURRENT (nA)
40
IB
I
0
−55
−40 −25 0 25 70 85 125
VCM > 1.0 V
T
, AMBIENT TEMPERATURE (°C)
A
Figure 5. Input Bias Current
versus Temperature
300
100
50
0
260
220
−50
−100
−150
, INPUT BIAS CURRENT (nA)
IB
I
−200
−250
0 6.0 8.0 10 12 105
2.0 4.0
V
, INPUT COMMON MODE VOLTAGE (V)
CM
VCC = 12 V
VEE = Gnd
T
= 25°C
A
180
VCC = +5.0 V
VEE = Gnd
140
, OPEN LOOP VOLTAGE GAIN (kV/V)
RL = 600
V
= 0.5 V to 4.5 V
A
VOL
100
O
−55 −40 −25 0 25 70 85 125
T
, AMBIENT TEMPERATURE (°C)
A
Figure 6. Input Bias Current
versus Common Mode Voltage
Figure 7. Open Loop Voltage Gain versus
Temperature
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MC33201, MC33202, MC33204, NCV33202, NCV33204
12
RL = 600
T
= 25°C
A
10
pp
8.0
6.0
4.0
, OUTPUT VOLTAGE (V )
O
2.0
V
0
Figure 8. Output Voltage Swing
12
pp
9.0
6.0
VCC = +6.0 V
VEE = −6.0 V
R
= 600
3.0
L
, OUTPUT VOLTAGE (V )
O
AV = +1.0
V
T
= 25°C
A
0
1.0 k 100 k 1.0 M10 k
±3.0 ±4.0 ±5.0 ±6.0
V
,VEE SUPPLY VOLTAGE (V)
CC
versus Supply V oltage
f, FREQUENCY (Hz)
T
= 125°C
A
VCC = +5.0 V
VEE = −5.0 V
, OUTPUT SATURATION VOLTAGE (V)
T
= 125°C
A
SAT
V
01520±1.0 ±2.0 105.0
IL, LOAD CURRENT (mA)
Figure 9. Output Saturation Voltage
versus Load Current
100
80
60
40
VCC = +6.0 V
VEE = −6.0 V
20
T
= −55° to +125°C
A
CMR, COMMON MODE REJECTION (dB)
0
10
100 1.0 k 10 k 100 k 1.0 M
T
= −55°C
A
T
= 25°C
A
T
= 25°C
A
T
= −55°C
A
f, FREQUENCY (Hz)
V
CC
VCC − 0.2 V
V
− 0.4 V
CC
+ 0.4 V
V
EE
V
+ 0.2 V
EE
V
EE
120
100
80
60
40
VCC = +6.0 V
20
VEE = −6.0 V
T
PSR, POWER SUPPLY REJECTION (dB)
= −55° to +125°C
A
0
10
Figure 10. Output Voltage
versus Frequency
PSR+
PSR−
100 1.0 k 10 k 100 k 1.0 M
f, FREQUENCY (Hz)
Figure 12. Power Supply Rejection
versus Frequency
Figure 11. Common Mode Rejection
versus Frequency
100
Source
80
60
Sink
40
20
, OUTPUT SHORT CIRCUIT CURRENT (mA)
SC
0
I
0 1.0 2.0 3.0 4.0 5.0 6.0
, OUTPUT VOLTAGE (V)
V
out
VCC = +6.0 V
VEE = −6.0 V
T
= 25°C
A
Figure 13. Output Short Circuit Current
versus Output Voltage
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MC33201, MC33202, MC33204, NCV33202, NCV33204
150
VCC = +5.0 V
VEE = Gnd
125
100
75
Source
Sink
50
25
, OUTPUT SHORT CIRCUIT CURRENT (mA)SR, SLEW RATE (V/ s)µ
0
SC
I
−55 −40 −25 25 70 1250 85 105 ±0
T
, AMBIENT TEMPERATURE (°C)
A
Figure 14. Output Short Circuit Current
versus Temperature
2.0
VCC = +2.5 V
VEE = −2.5 V
V
= ±2.0 V
O
1.5
1.0
0.5
+Slew Rate
−Slew Rate
2.0
1.6
1.2
0.8
0.4
, SUPPLY CURRENT PER AMPLIFIER (mA)
CC
0
I
Figure 15. Supply Current per Amplifier
versus Supply Voltage with No Load
4.0
VCC = +2.5 V
VEE = −2.5 V
f = 100 kHz
3.0
2.0
1.0
T
= 125°C
A
T
= 25°C
A
T
= −55°C
A
±1.0 ±2.0 ±3.0 ±4.0 ±5.0 ±6.0
V
, VEE, SUPPLY VOLTAGE (V)
CC
0
−55 −40 −25 25 70 1250 85 105 −55 −40 −25 25 70 1250 85 105
T
, AMBIENT TEMPERATURE (°C)
A
Figure 16. Slew Rate
versus Temperature
70
50
V
= ±6.0 V
S
T
= 25°C
A
R
= 600
L
30
10
1A − Phase, CL = 0 pF
1B − Gain, CL = 0 pF
−10
2A − Phase, CL = 300 pF
VOL
2B − Gain, CL = 300 pF
A , OPEN LOOP VOLTAGE GAIN (dB)
2A
2B
1B
−30
10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
40
80
120
1A
160
200
240
Figure 18. Voltage Gain and Phase
versus Frequency
GBW, GAIN BANDWIDTH PRODUCT (MHz)
0
, AMBIENT TEMPERATURE (°C)
T
A
Figure 17. Gain Bandwidth Product
versus Temperature
70
50
30
10
1A − Phase, V
1B − Gain, V
−10
, EXCESS PHASE (DEGREES)
2A − Phase, V
VOL
2B − Gain, V
A , OPEN LOOP VOLTAGE GAIN (dB)
= ±6.0 V
S
= ±6.0 V
S
= ±1.0 V
S
= ±1.0 V
S
−30
10 k 100 k 1.0 M 10 M
f, FREQUENCY (Hz)
CL = 0 pF
T
A
R
2A
2B
= 25°C
= 600
L
Figure 19. Voltage Gain and Phase
versus Frequency
1B
1A
40
80
120
160
200
, EXCESS PHASE (DEGREES)
240
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MC33201, MC33202, MC33204, NCV33202, NCV33204
70
60
50
VCC = +6.0 V
40
VEE = −6.0 V
RL = 600
30
CL = 100 pF
20
, PHASE MARGIN (DEGREES)
M
10
0
−55 −40 −25 25 70 1250 85 105 10
, AMBIENT TEMPERATURE (°C)
T
A
Phase Margin
Gain Margin
70
60
50
40
30
20
10
0
Figure 20. Gain and Phase Margin
versus Temperature
80
70
Phase Margin
60
Gain Margin
50
40
30
20
, PHASE MARGIN (DEGREES)
M
10
0
10 100 1.0 k 100 1.0 k 10 k
CL, CAPACITIVE LOAD (pF)
VCC = +6.0 V
VEE = −6.0 V
RL = 600
AV = 100
T
= 25°C
A
16
14
12
10
8.0
6.0
4.0
2.0
0
75
60
45
30
, GAIN MARGIN (dB)
M
A
15
, PHASE MARGIN (DEGREES)
M
0
Phase Margin
VCC = +6.0 V
VEE = −6.0 V
T
= 25°C
A
RT, DIFFERENTIAL SOURCE RESISTANCE ()
versus Differential Source Resistance
150
120
90
60
, GAIN MARGIN (dB)
M
A
30
CS, CHANNEL SEPARATION (dB)
0
VCC = +6.0 V
VEE = −6.0 V
VO = 8.0 V
T
= 25°C
A
Gain Margin
100 1.0 k 10 k 100 k
Figure 21. Gain and Phase Margin
AV = 100
AV = 10
pp
f, FREQUENCY (Hz)
75
60
45
30
, GAIN MARGIN (dB)
M
15
A
0
Figure 22. Gain and Phase Margin
versus Capacitive Load
10
VCC = +5.0 V
T
= 25°C
A
VO = 2.0 V
1.0
AV = 1000
AV = 100
0.1
AV = 10
0.01
AV = 1.0
THD, TOTAL HARMONIC DISTORTION (%)
0.001
10 100 1.0 k 100 k
VEE = −5.0 V
RL = 600
pp
f, FREQUENCY (Hz)
Figure 24. Total Harmonic Distortion
versus Frequency
50
40
30
20
10
0
n
10
e , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz)
Figure 25. Equivalent Input Noise Voltage
Figure 23. Channel Separation
versus Frequency
VCC = +6.0 V
VEE = −6.0 V
T
= 25°C
A
Noise Voltage
Noise Current
100 10 k 100 k10 k 1.0 k
f, FREQUENCY (Hz)
and Current versus Frequency
5.0
4.0
3.0
2.0
1.0
0
n
i , INPUT REFERRED NOISE CURRENT (pA/ Hz)
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MC33201, MC33202, MC33204, NCV33202, NCV33204
DETAILED OPERATING DESCRIPTION
General Information
The MC33201/2/4 family of operational amplifiers are
unique in their ability to swing rail−to−rail on both the input
and the output with a completely bipolar design. This offers
low noise, high output current capability and a wide
common mode input voltage range even with low supply
voltages. Operation is guaranteed over an extended
temperature range and at supply voltages of 2.0 V, 3.3 V and
5.0 V and ground.
Since the common mode input voltage range extends from
V
to VEE, it can be operated with either single or split
CC
voltage supplies. The MC33201/2/4 are guaranteed not to
latch or phase reverse over the entire common mode range,
however, the inputs should not be allowed to exceed
maximum ratings.
VCC = +6.0 V
VEE = −6.0 V
RL = 600
CL = 100 pF
T
= 25°C
A
Circuit Information
Rail−to−rail performance is achieved at the input of the
amplifiers by using parallel NPN−PNP differential input
stages. When the inputs are within 800 mV of the negative
rail, the PNP stage is on. When the inputs are more than 800
mV greater than V
, the NPN stage is on. T his s witching of
EE
input pairs will cause a reversal of input bias currents (see
Figure 6). Also, slight differences in offset voltage may be
noted between the NPN and PNP pairs. Cross−coupling
techniques have b een u sed t o k eep t his c hange to a m inimum.
In addition to its rail−to−rail performance, the output stage
is current boosted to provide 80 mA of output current,
enabling the op amp to drive 600 loads. Because of this
high output current capability, care should be taken not to
exceed the 150°C maximum junction temperature.
VCC = +6.0 V
VEE = −6.0 V
RL = 600
CL = 100 pF
T
= 25°C
A
, OUTPUT VOLTAGE (2.0 mV/DIV)
O
V
t, TIME (5.0 s/DIV)
Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response
VCC = +6.0 V
VEE = −6.0 V
RL = 600
CL = 100 pF
AV = 1.0
T
= 25°C
A
, OUTPUT VOLTAGE (2.0 V/DIV)V
O
Figure 28. Large Signal Transient Response
Surface mount board layout is a c ritical p ortion o f t he total
design. The f ootprint f or t he s emiconductor p ackages m ust b e
the correct size to ensure proper solder connection interface
, OUTPUT VOLTAGE (50 mV/DIV)V
O
t, TIME (10 s/DIV)
t, TIME (10 s/DIV)
between the board and the package. With the correct pad
geometry , the packages will self−align when subjected to a
solder reflow process.
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MC33201, MC33202, MC33204, NCV33202, NCV33204
ORDERING INFORMATION
Operational
Amplifier Function
Single
Dual
Dual
Quad
*NCV33202 and NCV33204 are qualified for automotive use.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Device
MC33201D
MC33201DR2 SOIC−8 2500 Units / Tape & Reel
MC33201P PDIP−8 50 Units / Rail
MC33201VD TA = −55° to 125°C SOIC−8 98 Units / Rail
MC33202D
MC33202DG
MC33202DR2 SOIC−8
MC33202DR2G
MC33202DMR2
MC33202P PDIP−8 50 Units / Rail
MC33202VD
MC33202VDR2 SOIC−8 2500 Units / Tape & Reel
NCV33202VDR2* SOIC−8 2500 Units / Tape & Reel
MC33202VP PDIP−8 50 Units / Rail
MC33204D
MC33204DR2 SO−14 2500 Units / Tape & Reel
MC33204DTB TSSOP−14 96 Units / Rail
MC33204DTBR2 TSSOP−14 2500 Units / Tape & Reel
MC33204P PDIP−14 25 Units / Rail
MC33204VD
MC33204VDR2 SO−14 2500 Units / Tape & Reel
NCV33204DR2* SO−14 2500 Units / Tape & Reel
NCV33204DTBR2* TSSOP−14 2500 Units / Tape & Reel
MC33204VP PDIP−14 25 Units / Rail
Operating
Temperature Range
TA= −40° to +105°C
TA= −40 ° to +105°C
TA= −40 ° to +105°C
TA = −55° to 125°C
TA= −40 ° to +105°C
TA = −55° to 125°C
Package Shipping
SOIC−8 98 Units / Rail
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Micro−8 4000 Units / Tape & Reel
SOIC−8 98 Units / Rail
SO−14 55 Units / Rail
SO−14 55 Units / Rail
98 Units / Rail
2500 Units / Tape & Reel
†
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10
MC33201, MC33202, MC33204, NCV33202, NCV33204
MARKING DIAGRAMS
SOIC−8
D SUFFIX
CASE 751
8
3320x
ALYW
1
SO−14
VD SUFFIX
CASE 751A
14
MC33204VD
AWLYWW
1
SOIC−8
VD SUFFIX
CASE 751
8
320xV
ALYW
1
*
*
14
MC33204P
AWLYYWW
1
PDIP−8
P SUFFIX
CASE 626
8
MC3320xP
AWL
YYWW
1
PDIP−14
P SUFFIX
CASE 646
14
x = 1 or 2
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W= Work Week
*This marking diagram applies to NCV3320x
PDIP−8
VP SUFFIX
CASE 626
8
MC33202VP
AWL
YYWW
1
PDIP−14
VP SUFFIX
CASE 646
MC33204VP
AWLYYWW
1
Micro−8
DM SUFFIX
CASE 846A
8
3202
AYW
1
14
MC33
204
ALYW
1
14
1
TSSOP−14
DTB SUFFIX
CASE 948G
14
1
SO−14
D SUFFIX
CASE 751A
MC33204D
AWLYWW
MC33
204V
ALYW
*
http://onsemi.com
11
NOTE 2
−T−
SEATING
PLANE
H
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−8
P, VP SUFFIX
CASE 626−05
ISSUE L
58
−B−
14
F
−A−
N
D
G
0.13 (0.005) B
C
K
M
M
A
T
M
L
J
M
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
N 0.76 1.01 0.030 0.040
INCHESMILLIMETERS
http://onsemi.com
12
−Y−
−Z−
MC33201, MC33202, MC33204, NCV33202, NCV33204
SOIC−8
D, VD SUFFIX
CASE 751−07
ISSUE AA
NOTES:
−X−
A
58
B
1
S
0.25 (0.010)
4
M
M
Y
K
G
C
SEATING
PLANE
0.10 (0.004)
H
D
0.25 (0.010) Z
M
Y
SXS
N
X 45
M
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
INCHES
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
4.0
0.155
1.270
0.050
SCALE 6:1
inches
mm
SOIC−8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
SEATING
PLANE
−T−
0.038 (0.0015)
PIN 1 ID
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
CASE 846A−02
−A−
K
G
−B−
D
8 PL
0.08 (0.003) A
C
H
J
ISSUE F
M
S
B
T DIM MIN MAX MIN MAX
S
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. 846A−01 OBSOLETE, NEW STANDARD 846A−02.
A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C −−− 1.10 −−− 0.043
D 0.25 0.40 0.010 0.016
G 0.65 BSC 0.026 BSC
H 0.05 0.15 0.002 0.006
J 0.13 0.23 0.005 0.009
K 4.75 5.05 0.187 0.199
L 0.40 0.70 0.016 0.028
INCHESMILLIMETERS
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
SOLDERING FOOTPRINT*
8X
1.04
0.041
6X
3.20
0.126
0.65
0.0256
0.38
0.015
8X
4.24
0.167
5.28
0.208
SCALE 8:1
Micro8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
inches
mm
http://onsemi.com
14
MC33201, MC33202, MC33204, NCV33202, NCV33204
PACKAGE DIMENSIONS
PDIP−14
P, VP SUFFIX
CASE 646−06
ISSUE M
14 8
B
17
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
Y14.5M, 1982.
FORMED PARALLEL.
−T−
SEATING
PLANE
−T−
SEATING
PLANE
N
HG
−A−
14 8
G
D 14 PL
0.25 (0.010) A
A
F
L
C
D
14 PL
0.13 (0.005)
K
J
M
M
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
0.290 0.310 7.37 7.87
M −−− 10 −−− 10
N 0.015 0.039 0.38 1.01
MILLIMETERSINCHES
SOIC−14
D, VD SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
−B−
71
M
7 PL
P
M
0.25 (0.010) B
X 45
C
R
K
S
B
T
S
M
M
F
J
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
http://onsemi.com
15
MC33201, MC33202, MC33204, NCV33202, NCV33204
ÇÇ
PACKAGE DIMENSIONS
TSSOP−14
DTB SUFFIX
CASE 948G−01
ISSUE O
0.10 (0.004)
−T−
SEATING
PLANE
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
−V−
B
−U−
N
F
7
DETAIL E
K
K1
J
J1
SECTION N−N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
−W−
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
INCHESMILLIMETERS
Micro8 is a trademark of International Rectifier.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your
local Sales Representative.
MC33201/D
16
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