ON Semiconductor MC26LS30 Technical data

MC26LS30

Dual Differential (EIA-422-A)/ Quad Single-Ended (EIA-423-A) Line Drivers

The MC26LS30 is a low power Schottky set of line drivers which can be configured as two differential drivers which comply with EIA–422–A standards, or as four single–ended drivers which comply with EIA–423–A standards. A mode select pin and appropriate choice of power supplies determine the mode. Each driver can source and sink currents in excess of 50 mA.

In the differential mode (EIA–422–A), the drivers can be used up to 10 Mbaud. A disable pin for each driver permits setting the outputs into a high impedance mode within a +10 V common mode range.

In the single–ended mode (EIA–423–A), each driver has a slew rate control pin which permits setting the slew rate of the output signal so as to comply with EIA–423–A and FCC requirements and to reduce crosstalk. When operated from symmetrical supplies (+5.0 V), the outputs exhibit zero imbalance

The MC26LS30 is available in a 16–pin surface mount package. Operating temperature range is –40° to +85°C.

16

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SO–16

D SUFFIX

1

CASE 751B

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W= Work Week

PIN CONNECTIONS

MARKING DIAGRAM

16

MC26LS30D

AWLYWW

1

• Operates as Two Differential EIA–422–A Drivers, or Four

Single–Ended EIA–423–A Drivers

• High Impedance Outputs in Differential Mode

• Short Circuit Current Limit In Both Source and Sink Modes

• ±10 V Common Mode Range on High Impedance Outputs

• ±15 V Range on Inputs

• Low Current PNP Inputs Compatible with TTL, CMOS, and MOS

Outputs

• Individual Output Slew Rate Control in Single–Ended Mode

• Replacement for the AMD AM26LS30 and National Semiconductor

DS3691

Representative Block Diagrams

Single–Ended Mode

EIA–423–A

Input A

Input B

Input C

Input D

SR-A

Out A

SR-B

Out B

SR-C

Out C

SR-D

Out D

Differential Mode

Enable AB

Input A

Input D

Enable CD

V

CC

VEE-8

EIA–422–A

-1

Out A

Out B

Out C

Out D

Gnd-5 Mode-4

V

Input A

Input B/

Enable AB

Mode

Gnd

Input C/

Enable CD

Input D

V

1

CC

2

3

4

5

6

7

8

EE

(Top View)

16

15

14

13

12

11

10

9

ORDERING INFORMATION

Device Package Shipping

MC26LS30D 48 Units/RailSO–16 MC26LS30DR2 2500 Tape & ReelSO–16

SR-A

Output A

Output B

SR-B

SR-C

Output C

Output D

SR-D

 Semiconductor Components Industries, LLC, 2000

July, 2000 – Rev. 1

1 Publication Order Number:

MC26LS30/D

MC26LS30

MAXIMUM OPERATING CONDITIONS (Pin numbers refer to SO–16 package only.)

Rating

Power Supply Voltage V

Input Voltage (All Inputs) V Applied Output Voltage when in High Impedance Mode

= 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1)

(V

CC

Output Voltage with VCC, VEE = 0 V V Output Current I Junction Temperature T

Devices should not be operated at these limits. The “Recommended Operating Conditions” table provides conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS

Rating Symbol Min Typ Max Unit

Power Supply Voltage (Differential Mode) V

Power Supply Voltage (Single–Ended Mode) V

Input Voltage (All Inputs) V Applied Output Voltage (when in High Impedance Mode) V Applied Output Voltage, V

= 0 V

CC

Output Current I Operating Ambient Temperature (See text) T

All limits are not necessarily functional concurrently.

V

Symbol Value Unit

–0.5, +7.0 –7.0, +0.5

–0.5, +20 Vdc

±15 Vdc

±15

Self limiting –

–65, +150 °C

5.0 0

+5.0 –5.0

CC EE

za zb

O

CC

V

EE

in

V

za

zb

O

J

+4.75

–0.5

+4.75 –5.25

in

0 – +15 Vdc –10 – +10 –10 – +10

–65 – +65 mA

A

–40 – +85 °C

+5.25

+0.3

+5.25 –4.75

Vdc

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MC26LS30

ELECTRICAL CHARACTERISTICS (EIA–422–A differential mode, Pin 4  0.8 V, –40°C T

V

= Gnd, unless otherwise noted. Pin numbers refer to SO–16 package only.)

EE

Characteristic

Output Voltage (see Figure 1)

Differential, R Differential, R Change in Differential Voltage, R Offset Voltage, R Change in Offset Voltage*, R

= ∞, VCC = 5.25 V

L

= 100 Ω, VCC = 4.75 V

L

= 100 Ω

L

= 100 Ω

L

= 100 Ω (Note 4.)

Output Current (each output)

Power Off Leakage, V High Impedance Mode, V

= 0, –10 V  VO  +10 V

CC

= 5.25 V, –10 V  VO  +10 V

CC

Short Circuit Current (Note 2.)

High Output Shorted to Pin 5 (T High Output Shorted to Pin 5 (–40°C  T Low Output Shorted to +6.0 V (T Low Output Shorted to +6.0 V (–40°C  T

= 25°C)

A

= 25°C)

A

+85°C)

A

 +85°C)

A

Inputs

Low Level Voltage High Level Voltage Current @ V Current @ V Current @ V Current, 0  V Clamp Voltage (I

= 2.4 V

in

= 15 V

in

= 0.4 V

in

 15 V, VCC = 0

in

= –12 mA)

in

Power Supply Current (VCC = +5.25 V, Outputs Open)

(0  Enable  V

CC

)

Symbol Min Typ Max Unit

V



OD1

V

OD2

∆V

OD2

V

OS

∆VOS

I

OLK

I

OZ

I

SC–

I

SC–

I

SC+

I

SC+

V

IL

V

IH

I

IH

I

IHH

I

IL

I

IX

V

IK

I

CC



–

2.0 – – –

–100 –100

–150 –150

60 50

–

2.0 – –

–200

–

–1.5

– 16 30

 85°C, 4.75 V  VCC  5.25 V,

A

4.2

2.6 10

2.5 10

0 0

–95

–

75

–

– – 0 0

–8.0

0 –

6.0 –

400

3.0

400

+100 +100

–60 –50 150 150

0.8 –

40

100

– – –

Vdc Vdc

mVdc

Vdc

mVdc

Vdc Vdc

Vdc

µA

mA

µA

mA

TIMING CHARACTERISTICS (EIA–422–A differential mode, Pin 4  0.8 V, T

unless otherwise noted.)

Characteristic

Differential Output Rise Time (Figure 3) t Differential Output Fall Time (Figure 3) t Propagation Delay Time – Input to Differential Output

Input Low to High (Figure 3) Input High to Low (Figure 3)

Skew Timing (Figure 3)

t

to t

PDH

Max to Min t Max to Min t

Enable Timing (Figure 4)

Enable to Active High Differential Output Enable to Active Low Differential Output Enable to 3–State Output From Active High Enable to 3–State Output From Active Low

1. All voltages measured with respect to Pin 5.

2. Only one output shorted at a time, for not more than 1 second.

3. Typical values established at +25°C, V

4. V

switched from 0.8 to 2.0 V.

in

5. Imbalance is the difference between V

 for Each Driver

PDL

Within a Package

PDH

Within a Package

PDL

= +5.0 V, VEE = –5.0 V.

CC

 with Vin  0.8 V and VO2 with Vin  2.0 V.

O2

= 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1. and 3.)

A

Symbol Min Typ Max Unit

r f

– 70 200 ns – 70 200 ns

ns

t

PDH

t

PDL

– –

90 90

200 200

ns

t

SK1

t

SK2

t

SK3

– – –

9.0

2.0

– – –

ns

t

PZH

t

PZL

t

PHZ

t

PLZ

– – – –

150 190

80

110

300 350 350 300

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3

MC26LS30

ELECTRICAL CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4  2.0 V, –40°C  T

|V

  5.25 V, (Notes 1. and 3.) unless otherwise noted).

EE

Characteristic

Output Voltage (VCC = VEE = 4.75 V)

Single–Ended Voltage, R Single–Ended Voltage, R Voltage Imbalance (Note 5.), R

= ∞ (Figure 2)

L

= 450 Ω, (Figure 2)

L

= 450 Ω

L

Slew Control Current (Pins 16, 13, 12, 9) I Output Current (Each Output)

Power Off Leakage, V

= VEE = 0, –6.0 V  VO  +6.0 V

CC

Short Circuit Current (Output Short to Ground, Note 2.)

 0.8 V (TA = 25°C)

V

in

 0.8 V (–40°C  TA  +85°C)

V

in

V

 2.0 V (TA = 25°C)

in

 2.0 V (–40°C  TA  +85°C)

V

in

Inputs

Low Level Voltage High Level Voltage Current @ V Current @ V Current @ V Current, 0  V Clamp Voltage (I

= 2.4 V

in

= 15 V

in

= 0.4 V

in

 15 V, VCC = 0

in

= –12 mA)

in

Power Supply Current (Outputs Open)

= +5.25 V, VEE = –5.25 V, Vin = 0.4 V

V

CC

Symbol Min Typ Max Unit

VO1 V

∆V

SLEW

I

OLK

I

SC+

I

SC+

I

SC–

I

SC–

V V

I

IHH

I I

V I

CC

I

EE



O2



O2

IL

IH

IL

IX

IK

4.0

3.6 –

– ±120 – µA

–100

60

50 –150 –150

–

2.0 – –

–200

–

–1.5

–

–22

 85°C, 4.75 V  V

A

4.2

3.95

0.05

0

80

–

–95

–

– – 0 0

–8.0

0 –

17

–8.0

6.0

0.4

+100

150 150 –60 –50

0.8 –

40

100

– – –

30

–

CC

,

Vdc

µA

mA

Vdc Vdc

µA

Vdc

mA

TIMING CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4  2.0 V, T

3.) unless otherwise noted.)

Characteristic

Output Timing (Figure 5)

Output Rise Time, C Output Fall Time, C Output Rise Time, C

Output Fall Time, C Rise Time Coefficient (Figure 16) C Propagation Delay Time, Input to Single Ended Output (Figure 5)

Input Low to High, C

Input High to Low, C Skew Timing, CC = 0 (Figure 5)

to t

t

PDH

Max to Min t

 for Each Driver

PDL

PDH PDL

1. All voltages measured with respect to Pin 5.

2. Only one output shorted at a time, for not more than 1 second.

3. Typical values established at +25°C, V

4. V

switched from 0.8 to 2.0 V.

in

5. Imbalance is the difference between V

= 0

C

= 0

C

= 50 pF

C

= 50 pF

C

= 0

C

= 0

C

Within a Package

= +5.0 V, VEE = –5.0 V.

CC

 with Vin  0.8 V and VO2 with Vin  2.0 V.

O2

= 25°C, VCC = 5.0 V, VEE = –5.0 V, (Notes 1. and

A

Symbol Min Typ Max Unit

t

r

t

f

t

r

t

f rt

– – – –

65 65

3.0

300 300

– –

ns

µs

– 0.06 – µs/pF

ns

t

PDH

t

PDL

– –

100 100

300 300

ns

t

SK4

t

SK5

t

SK6

– – –

15

2.0

5.0

– – –

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4

Differential

+5.0

Gnd

00010000010110100

(EIA 422 A)

001X0100111Z0Z001

00X1100010Z1Z0011

00100000011001100

000100011X01100Z1

S g e ded

50

010000000100000

(EIA 423 A)

11100100001001000

11001001000010010

11000010010000100

V

in

(0.8 or 2.0 V)

Mode = 0

MC26LS30

T able 1

Inputs Outputs

Operation V

CC

Differential +5.0 Gnd 0 0 0 0 0 0 1 1 0 (EIA–422–A)

Single–Ended +5.0 –5.0 1 0 0 0 0 0 0 0 0 (EIA–423–A)

X 0 X X X X X X Z Z Z Z

X = Don’t Care Z = High Impedance (Off)

V

CC

/2

R

L

V

OD2

RL/2

V

Mode A B C D A B C D

EE

1

V

CC

V

in

(0.8 or 2.0 V)

V

OS

Mode = 1

V

EE

1 1 0 1

Z

0 0 0 1

R

C

L

V

O

Figure 1. Differential Output Test Figure 2. Single–Ended Output Test

V

CC

V

in

100

500 pF

V

OD

S.G.

NOTES:

1. S.G. set to: f  1.0 MHz; duty cycle = 50%; t

2. t

= t

SK1

3. t

4. t

PDH–tPDL

computed by subtracting the shortest t

SK2

computed by subtracting the shortest t

SK3

 for each driver.

Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay

, tf,  10 ns.

r

from the longest t

PDH

from the longest t

PDL

+3.0 V

V

in

1.5 V

t

PDH

90%

50%

V

out

10%

t

r

of the 2 drivers within a package.

PDH

of the 2 drivers within a package.

PDL

1.5 V

t

f

t

0 V

PDL

90%

50%

10%

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5

MC26LS30

V

CC

V

0 or 3.0 V

V

in

S.G.

En

500 pF

450 Ω

R

L

V

SS

in

(Vin = Hi)

Output Current

= Lo)

(V

in

NOTES:

1. S.G. set to: f  1.0 MHz; duty cycle = 50%; t

, tf,  10 ns.

r

2. Above tests conducted by monitoring output current levels.

Figure 4. Differential Mode Enable Timing

V

CC

C

Vin

V

EE

S.G.

NOTES:

1. S.G. set to: f  100 kHz; duty cycle = 50%; t

2. t

= t

SK4

3. t

4. t

PDH–tPDL

computed by subtracting the shortest t

SK5

computed by subtracting the shortest t

SK6

C

450

 for each driver.

500 pF

, tf, 10 ns.

r

PDH PDL

V

O

from the longest t

1.5 V

t

PHZ

PLZ

0.1 VSS/R

L

0.1 V

SS/RL

V

in

1.5 V

t

PDH

90%

50%

V

out

10%

of the 4 drivers within a package.

PDH

of the 4 drivers within a package.

PDL

+3.0 V

1.5 V

0 V

t

PZH

VSS/R

L

t

PZL

0.5 VSS/R

L

+2.5 V

1.5 V 0 V

t

PDL

90%

50%

10%

t

r

t

f

Figure 5. Single–Ended Mode Rise/Fall Time and Data Propagation Delay

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