MC14584B
Hex Schmitt Trigger
The MC14584B Hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity to “square up” slowly changing waveforms.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Can Be Used to Replace MC14069UB
• For Greater Hysteresis, Use MC14106B which is Pin−for−Pin
Replacement for CD40106B and MM74Cl4
• Pb−Free Packages are Available
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14
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
1
MARKING
DIAGRAMS
MC14584BCP
AWLYYWWG
14584BG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
Vin, V
Iin, I
P
T
T
T
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and V
to the range VSS v (Vin or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
(DC or Transient)
Input or Output Current
out
D
A
stg
L
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range −55 to +125 °C
Storage Temperature Range −65 to +150 °C
Lead Temperature
(8−Second Soldering)
) v VDD.
out
)
SS
−0.5 to VDD + 0.5 V
± 10 mA
500 mW
260 °C
should be constrained
out
14
TSSOP−14
DT SUFFIX
CASE 948G
14
SOEIAJ−14
F SUFFIX
CASE 965
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
14
584B
ALYWG
G
1
MC14584B
ALYWG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1 Publication Order Number:
MC14584B/D
MC14584B
PIN ASSIGNMENT
1
IN 1
IN 2
IN 3
V
2
3
4
6
7
SS
OUT 1
OUT 2
OUT 3
14
V
DD
13
IN 6
12
OUT 6
11
IN 5
105
OUT 5
9
IN 4
8
OUT 4
EQIVALENT CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
LOGIC DIAGRAM
1
3
5
9
11
13
VDD = PIN 14
VSS = PIN 7
2
4
6
8
10
12
ORDERING INFORMATION
Device Package Shipping
MC14584BCP PDIP−14
MC14584BCPG PDIP−14
(Pb−Free)
MC14584BD SOIC−14
MC14584BDG SOIC−14
(Pb−Free)
MC14584BDR2 SOIC−14
MC14584BDR2G SOIC−14
(Pb−Free)
MC14584BDTR2 TSSOP−14*
MC14584BDTR2G TSSOP−14*
MC14584BF SOEIAJ−14
MC14584BFG SOEIAJ−14
(Pb−Free)
MC14584BFEL SOEIAJ−14
MC14584BFELG SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
25 Units / Rail
55 Units / Rail
2500 / Tape & Reel
50 Units / Rail
2000 / Tape & Reel
†
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2
MC14584B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
DD
Characteristic Symbol
Output Voltage “0” Level
= V
V
in
DD
Vin = 0 “1” Level V
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current I
Input Capacitance
Vdc
V
OL
5.0
10
15
OH
5.0
10
15
I
OH
5.0
5.0
10
15
I
OL
5.0
10
15
in
C
in
15 − ± 0.1 − ±0.00001 ±0.1 − ± 1.0
Min Max Min Typ
4.95
9.95
14.95
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
− − − − 5.0 7.5 − − pF
)
SS
− 55_C 25_C 125_C
(2)
Max Min Max
−
0.05
−
0.05
−
0.05
−
−
−
−
−
−
−
−
−
−
−
−
−
4.95
9.95
14.95
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
0
0
0
5.0
10
15
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
−
−
−
4.95
9.95
14.95
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
(Vin = 0)
Quiescent Current
(Per Package)
Total Supply Current
(3) (4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
I
DD
I
T
5.0
10
15
5.0
10
15
−
0.25
−
−
0.5
1.0
−
0.0005
−
0.0010
−
0.0015
IT = (1.8 mA/kHz) f + I
IT = (3.6 mA/kHz) f + I
IT = (5.4 mA/kHz) f + I
0.25
0.5
1.0
DD
DD
DD
−
−
−
7.5
15
30
buffers switching)
Hysteresis Voltage VH
Threshold Voltage
Positive−Going
Negative−Going V
(5)
5.0
10
15
V
T+
5.0
10
15
T–
5.0
10
15
0.27
0.36
0.77
1.9
3.4
5.2
1.6
3.0
4.5
1.0
1.3
1.7
3.5
7.0
10.6
3.3
6.7
9.7
0.25
0.3
0.6
1.8
3.3
5.2
1.6
3.0
4.6
0.6
0.7
1.1
2.7
5.3
8.0
2.1
4.6
6.9
1.0
1.2
1.5
3.4
6.9
10.5
3.2
6.7
9.8
0.21
0.25
0.50
1.7
3.2
5.2
1.5
3.0
4.7
1.0
1.2
1.4
3.4
6.9
10.5
3.2
6.7
9.9
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
5. VH = VT+ – VT– (But maximum variation of VH is specified as less than V
T + max
– V
T – min
).
Unit
Vdc
Vdc
mAdc
mAdc
mAdc
mAdc
mAdc
Vdc
Vdc
Vdc
SWITCHING CHARACTERISTICS (C
= 50 pF, T
L
Characteristic Symbol
Output Rise Time t
Output Fall Time t
Propagation Delay Time t
= 25_C)
A
PLH
TLH
THL
, t
PHL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
Min Typ
−
−
−
−
−
−
−
−
−
100
50
40
100
50
40
125
50
40
(6)
Max Unit
200
100
80
200
100
80
250
100
80
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
ns
ns
ns
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