ON Semiconductor MC14513B Technical data

MC14513B

BCD-To-Seven Segment
Latch/Decoder/Driver

CMOS MSI
(Low–Power Complementary MOS)

The MC14513B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output d rivers in a s ingle m onolithic s tructure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, a nd h as o utput d rive c apability. Lamp
test (LT

), blanking (BI), and latch enable ( LE) i nputs a re us ed t o t est t he
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD c ode, respectively. The Ripple Blanking Input (RBI) and
Ripple Blanking Output (RBO) can be used to suppress either leading
or trailing zeroes. It can be used with seven–segment light emitting
diodes (LED), incandescent, fluorescent, gas d ischar ge, o r l iquid c rystal
readouts either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.

• Low Logic Circuit Power Dissipation

• High–current Sourcing Outputs (Up to 25 mA)

• Latch Storage of Binary Input

• Blanking Input

• Lamp Test Provision

• Readout Blanking on all Illegal Input Combinations

• Lamp Intensity Modulation Capability

• Time Share (Multiplexing) Capability

• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B

• Supply Voltage Range = 3.0 V to 18 V

• Capable of Driving Two Low–Power TTL Loads, One Low–power

Schottky TTL Load to Two HTL Loads Over the Rated Temperature
Range.

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

V

P

T

T

I

OHmax

P

OHmax

DD

stg

DC Supply Voltage Range –0.5 to +18.0 V
Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V

in

I DC Current Drain per Input Pin 10 mA

Power Dissipation,

D

A

per Package
Operating Temperature Range –55 to +125 °C
Storage Temperature Range –65 to +150 °C
Maximum Continuous Output

Drive Current (Source) per Output
Maximum Continuous Output

Power (Source) per Output

(2.)

(3.)

(1.)

)

SS

500 mW

25 mA

50 mW

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MARKING

DIAGRAMS

18

PDIP–18

P SUFFIX

CASE 707

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

MC14513BCP

AWLYYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14513BCP PDIP–18 20/Rail

This device contains protection circuitry to protect
the inputs against damage due to high static voltages
or electric fields. However, it is advised that normal
precautions be taken to avoid application of any volt­age higher than maximum rated voltages to this high–
impedance circuit. A destructive high current mode
may occur if V
range V

Due to the sourcing capability of this circuit, dam­age can occur to the device if V
outputs are shorted to V
Maximum Ratings).

Unused inputs must always be tied to an appropri­ate logic voltage level (e.g., either V

1. Maximum Ratings are those values beyond which

damage to the device may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C
From 65C To 125C

3. P

OHmax

and V

in

 (Vin or V

SS

= IOH (VDD – VOH)

are not constrained to the

out

)  VDD.

out

is applied, and the

DD

and are at a logical 1 (See

SS

or VDD).

SS

 Semiconductor Components Industries, LLC, 2000

August, 2000 – Rev. 4

1 Publication Order Number:

MC14513B/D

MC14513B

PIN ASSIGNMENT

V

1

B

2

C

3

LT

4

BI

LE

5

6

D

7

A

8

RBI

9

V

SS

DISPLAY

0123456789

TRUTH TABLE

Inputs Outputs

RBI LE BI

X X X 0 XXXX + 1111111 8
X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank

0 0 1 1 0000 0 1111110 0
X 0 1 1 0 0 01 0 0110000 1

X 0 1 1 0010 0 1101101 2
X 0 1 1 0011 0 1111001 3
X 0 1 1 0100 0 0110011 4
X 0 1 1 0101 0 1011011 5

X 0 1 1 0110 0 1011111 6
X 0 1 1 0111 0 1110000 7
X 0 1 1 1000 0 1111111 8
X 0 1 1 1001 0 1111011 9
X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank

X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank
X 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank

X 1 1 1 X X X X † * *

X = Don’t Care
†RBO = RBI (D
*Depends upon the BCD code previously applied when LE = 0

LT D C B A RBO a b c d e f g Display

C B A), indicated by other rows of table

18

DD

f

17

g

16

a

15

b

14

c

13

d

12

e

11

RBO

10

fg

e

d

a

b

c

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2

MC14513B

V

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

– 55C 25C 125C

Min Max Min Typ

—
—
—

4.1

9.1

14.1

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

—

3.9
—

3.4
—

—

9.0
—

8.6
—

—
14
—

13.6
—

Characteristic Symbol

Output Voltage — Segment Outputs

“0” Level

V

= VDD or 0

in

“1” Level

= 0 or V

V

in

DD

Output Voltage — RBO Output

“0” Level

V

= VDD or 0

in

“1” Level

= 0 or V

V

in

Input Voltage

(V

O

(V

O

(V

O

DD

(4.)

= 3.8 or 0.5 Vdc)
= 8.8 or 1.0 Vdc)
= 13.8 or 1.5 Vdc)

“0” Level

(VO = 0.5 or 3.8 Vdc) “1” Level

= 1.0 or 8.8 Vdc)

(V

O

(V

= 1.5 or 13.8 Vdc)

O

Output Drive Voltage — Segments

(I

= 0 mA) Source

OH

= 5.0 mA)

(I

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

(I

= 20 mA)

OH

(I

= 25 mA)

OH

(IOH = 0 mA)
(I

= 5.0 mA)

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

= 20 mA)

(I

OH

(I

= 25 mA)

OH

(IOH = 0 mA)
(I

= 5.0 mA)

OH

(I

= 10 mA)

OH

(I

= 15 mA)

OH

(I

= 20 mA)

OH

= 25 mA)

(I

OH

DD

Vdc

V

OL

5.0
10
15

V

OH

5.0
10
15

V

OL

5.0
10
15

V

OH

5.0
10
15

V

IL

5.0
10
15

V

IH

5.0
10
15

V

OH

5.0 4.1

10 9.1

15 14.1

SS

)

0.05

0.05

0.05

0.05

0.05

0.05

—
—
—

—
—
—

1.5

3.0

4.0
—

—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—

4.1

9.1

14.1

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

4.1
—

3.9
—

3.4
—

9.1
—

9.0
—

8.6
—

14.1
—
14
—

13.6
—

0
0
0

5.0
10
15

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

4.57

4.24

4.12

3.94

3.70

3.54

9.58

9.26

9.17

9.04

8.90

8.75

14.59

14.27

14.18

14.07

13.95

13.80

(4.)

Max Min Max

0.05

0.05

0.05
—

—
—

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0
—

—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—

4.1

9.1

14.1

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

4.1
—

3.5
—

3.0
—

9.1
—

8.6
—

8.2
—

14.1
—

13.6
—

13.2
—

0.05

0.05

0.05
—

—
—

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0
—

—
—

—
—
—
—
—
—

—
—
—
—
—
—

—
—
—
—
—
—

Unit

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

Vdc

(continued)

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3

MC14513B

V

ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to V

DD

Characteristic Symbol

Output Drive Current — RBO Output

(V

= 2.5 V) Source

OH

(V

= 9.5 V)

OH

= 13.5 V)

(V

OH

(VOL = 0.4 V) Sink

= 0.5 V)

(V

OL

(V

= 1.5 V)

OL

Output Drive Current — Segments

(V

= 0.4 V) Sink

OL

= 0.5 V)

(V

OL

(V

= 1.5 V)

OL

Input Current I
Input Capacitance C
Quiescent Current

(Per Package) V

= 0 µA

I

out

Total Supply Current

= 0 or VDD,

in

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

= 50 pF on all outputs, all

L

I

OH

I

OL

I

OL

in

I

DD

I

Vdc

5.0
10
15

5.0
10
15

5.0
10
15

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

in

— — — — 5.0 7.5 — — pF

5.0
10
15

T

5.0
10
15

buffers switching)

4. Noise immunity specified for worst–case input combination.
Noise Margin for both “1” and “0” level =

1.0 Vdc min @ V

2.0 Vdc min @ V

2.5 Vdc min @ V

5. The formulas given are for the typical characteristics only at 25C.

= 5.0 Vdc

DD

= 10 Vdc

DD

= 15 Vdc

DD

6. To calculate total supply current at loads other than 50 pF:

) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf

I

T(CL

where: I

is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

T

– 55C 25C 125C

Min Max Min Typ

– 0.40
– 0.21
– 0.81

0.18

0.47

1.80

0.64

1.6

4.2

—
—
—

—
—
—

—
—
—

—
—
—

5.0
10
20

– 0.32
– 0.17
– 0.66

)

SS

(4.)

– 0.64
– 0.34
– 1.30

0.15

0.38

1.50

0.51

1.3

3.4

—
—
—

0.29

0.75

2.90

0.88

2.25

8.8

0.005

0.010

0.015

IT = (1.9 µA/kHz) f + I
IT = (3.8 µA/kHz) f + I
IT = (5.7 µA/kHz) f + I

Max Min Max

—

5.0

DD
DD
DD

—
—

—
—
—

—
—
—

10
20

– 0.22
– 0.12
– 0.46

0.10

0.26

1.0

0.36

0.9

2.4

—
—
—

—
—
—

—
—
—

—
—
—

150
300
600

Unit

mAdc

mAdc

mAdc

µAdc

µAdc

Input LE and RBI low, and Inputs D, BI and LT high.
f in respect to a system clock.
All outputs connected to respective C

20 ns

A, B, AND C

90%

50%
1

10%

20 ns

loads.

L

V

DD

V

SS

2f

ANY OUTPUT

50% DUTY CYCLE

50%

V

OH

V

OL

Figure 1. Dynamic Power Dissipation Signal Waveforms

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4

MC14513B

V

PLH L

PLH L

SWITCHING CHARACTERISTICS

(7.)

(C

= 50 pF, T

L

= 25C)

A

Characteristic Symbol

Output Rise Time — Segment Outputs t

Output Rise Time — RBO Output t

Output Fall Time — Segment Outputs

t

= (1.5 ns/pF) CL + 50 ns

THL

= (0.75 ns/pF) CL + 37.5 ns

t

THL

t

= (0.55 ns/pF) CL + 37.5 ns

THL

(7.)

Output Fall Time — RBO Outputs

t

= (3.25 ns/pF) CL + 107.5 ns

THL

= (1.35 ns/pF) CL + 67.5 ns

t

THL

t

= (0.95 ns/pF) CL + 62.5 ns

THL

Propagation Delay Time — A, B, C, D Inputs

t

= (0.40 ns/pF) CL + 620 ns

PLH

= (0.25 ns/pF) CL + 237.5 ns

t

PLH

t

= (0.20 ns/pF) CL + 165 ns

PLH

t

= (1.3 ns/pF) CL + 655 ns

PHL

t

= (0.60 ns/pF) CL + 260 ns

PHL

= (0.35 ns/pF) CL + 182.5 ns

t

PHL

Propagation Delay Time — RBI and BI Inputs

t

= (1.05 ns/pF) CL + 547.5 ns

PLH

= (0.45 ns/pF) CL + 177.5 ns

t

PLH

t

= (0.30 ns/pF) CL + 135 ns

PLH

t

= (0.85 ns/pF) CL + 442.5 ns

PHL

= (0.45 ns/pF) CL + 177.5 ns

t

PHL

t

= (0.35 ns/pF) CL + 142.5 ns

PHL

Propagation Delay Time — LT Input

t

= (0.45 ns/pF) CL + 290.5 ns

PLH

= (0.25 ns/pF) CL + 112.5 ns

t

PLH

t

= (0.20 ns/pF) CL + 80 ns

PLH

t

= (1.3 ns/pF) CL + 248 ns

PHL

= (0.45 ns/pF) CL + 102.5 ns

t

PHL

t

= (0.35 ns/pF) CL + 72.5 ns

PHL

(7.)

(7.)

(7.)

Setup Time t

Hold Time t

Latch Enable Pulse Width t

7. The formulas given are for the typical characteristics only.

TLH

TLH

t

THL

t

THL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

su

h

WL(LE)

DD

Vdc

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

All Types

Min Typ Max

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

100

40
30

60
40
30

520
220
130

40
30
25

480
240
190

125

75
65

270
135
110

640
250
175

720
290
200

600
200
150

485
200
160

313
125

90

313
125

90
—

—
—

—
—
—

260
110

65

80
60
50

960
480
380

250
150
130

540
270
220

1280

500
350

1440

580
400

750
300
220

970
400
320

625
250
180

625
250
180

—
—
—

—
—
—

—
—
—

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

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5

MC14513B

20 ns

INPUT C

t

PLH

t

90%
50%

10%

PHL

20 ns

V

V

V

DD

SS

OH

OUTPUT g

V

OL

t

TLH

t

THL

a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI

20 ns

90%

INPUT C

50%

10%

t

PLH

OUTPUT RBO

50%

t

PHL

90%

10%

t

TLH

t

THL

b. Inputs A, B, D and LE low, and Inputs RBI, BI

20 ns

V

DD

V

SS

V

OH

V

OL

and L T high.

and L T high.

20 ns

V

V

V

LE

INPUT C

50%

90%

50%

10%

t

t

su

h

V

V

OUTPUT g

V

c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI

20 ns

V

DD

V

SS

LE

20 ns

t

WL(LE)

90%

50%

10%

d. Pulse Width: Data DCBA strobed into latches.

DD

SS

DD

SS

OH

OL

and L T high.

Figure 2. Dynamic Signal Waveforms

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6

MC14513B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIGHT EMITTING DIODE (LED) READOUT

V

DD

COMMON

CATHODE LED

≈ 1.7 V

V

SS

INCANDESCENT READOUT FLUORESCENT READOUT

V

DD

V

DD

V

DD

COMMON

ANODE LED

V

SS

V

DD

≈ 1.7 V

* *

DIRECT
(LOW BRIGHTNESS)

V

SS

V

SS

VSS OR APPROPRIATE
VOLTAGE BELOW V

GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) READOUT

V

DD

APPROPRIATE

VOLTAGE

V

DD

1/4 OF MC14070B

EXCITATION
(SQUARE WAVE,
V

SS

FILAMENT
(SUPPLY)

TO VDD)

.

SS

V

SS

**A filament pre–warm resistor is recommended to reduce

filament thermal shock and increase the effective cold
resistance of the filament.

Direct dc drive of LC’s not recommended for life of LC readouts.

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7

V

SS

A7

MC14513B

LOGIC DIAGRAM

BI4

15a

14b

13c

B1

C2

D6

LE5

RBI8

LT

30

10RBO

12d

11e

17f

16g

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8

CONNECT TO

(1)

V

DD

a- ---g-

RBI RBO

DCB A

MC14513B

TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

DISPLAYS

agagagagag

----- ----- ----- ----- -----

RBI RBI

1

DCBA DCBA DCBA DCBA DCBA

RBO

1000

RBO RBO RBO RBO

RBI RBI RBI

0

MC14513B MC14513B MC14513B MC14513B MC14513B

0000

(0)

0101

(5)

0000

(0)

0001

(1)

INPUT
CODE

MC14513B

0000

(0)

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS

----- ----- ----- ----- ----- -----

ag

0

RBO

DC B A

01 01

RBI

MC14513B

(5)

agagagagag

RBO

0

DC B A DC BA DCB A DC BA DC BA

0000

RBI

0011

MC14513B MC14513B MC14513B MC14513B MC14513B

0001

(0)

RBI RBI RBI RBI

(1)

RBORBO

0011

(3)

RBO RBO

0000

(0)

0011

0000

(0)

(3)

CONNECT TO

VDD (1)

INPUT CODE

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9

MC14513B

PACKAGE DIMENSIONS

PDIP–18

P SUFFIX

PLASTIC DIP PACKAGE

CASE 707–02

ISSUE C

NOTES:

J

18

1

A

10

B

9

L

M

C

K

N

F

D

H

G

SEATING
PLANE

1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 22.22 23.240.875 0.915
B 6.10 6.600.240 0.260
C 3.56 4.570.140 0.180
D 0.36 0.560.014 0.022
F 1.27 1.780.050 0.070
G 2.54 BSC0.100 BSC
H 1.02 1.520.040 0.060

J 0.20 0.300.008 0.012
K 2.92 3.430.115 0.135
L 7.62 BSC0.300 BSC
M 0 15 0 15

 

N 0.51 1.020.020 0.040

MILLIMETERSINCHES

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10

Notes

MC14513B

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11

MC14513B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (Mon–Fri 2:30pm to 7:00pm CET)

Email: ONlit–[e-mail]

French Phone: [phone] (Mon–Fri 2:00pm to 7:00pm CET)

Email: ONlit–[e-mail]

English Phone: [phone] (Mon–Fri 12:00pm to 5:00pm GMT)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy, UK

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:
001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

http://onsemi.com

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