
MC14099B
8−Bit Addressable Latches
The MC14099B is an 8−bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read
Enable.
A Master Reset capability is available on both parts.
or Chip
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MARKING
DIAGRAMS
Features
• Serial Data Input
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation, per Package
D
Ambient Temperature Range −55 to +125 °C
A
Storage Temperature Range −65 to +150 °C
stg
Lead Temperature
L
Parameter Value Unit
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
)
SS
−0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
PDIP−16
P SUFFIX
CASE 648
SOIC−16
DW SUFFIX
CASE 751G
SOEIAJ−16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
16
MC14099BCP
AWLYYWW
1
16
14099B
AWLYYWW
1
16
MC14099B
AWLYWW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
(Vin or V
SS
or VDD). Unused outputs must be left open.
SS
) VDD.
out
and V
in
should be constrained
out
1 Publication Order Number:
MC14099B/D

MC14099B
PIN ASSIGNMENT
1
Q7
DATA
2
3
4
RESET
WRITE
DISABLE
A0
A1
6
A2
7
8
V
SS
ORDERING INFORMATION
Device Package Shipping
MC14099BCP PDIP−16 500 Units / Rail
MC14099BCPG PDIP−16
MC14099BDW SOIC−16 WB 47 Units / Rail
MC14099BDWG SOIC−16 WB
MC14099BDWR2 SOIC−16 WB 1000 Units / Tape & Reel
MC14099BDWR2G SOIC−16 WB
MC14099BFEL SOEIAJ−16 2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
16
V
DD
15
Q6
14
Q5
13
Q4
125
Q3
11
Q2
10
Q1
9
Q0
WRITE DISABLE
RESET
DATA
A0
A1
A2
MC14099B
5
6
DECODER
7
V
= 16
DD
V
= 8
SS
4
3
8
2
8
LATCHES
9
Q0
10
Q1
11
Q2
12
Q3
13
Q4
14
Q5
15
Q6
1
Q7
†
500 Units / Rail
(Pb−Free)
47 Units / Rail
(Pb−Free)
1000 Units / Tape & Reel
(Pb−Free)
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2

MC14099B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
Characteristic
ОООООООО
Output Voltage “0” Level
V
= VDD or 0
in
ОООООООО
“1” Level
V
= 0 or V
in
ОООООООО
DD
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
ОООООООО
O
= 9.0 or 1.0 Vdc)
(V
O
ОООООООО
= 13.5 or 1.5 Vdc)
(V
O
“1” Level
= 0.5 or 4.5 Vdc)
(V
ОООООООО
O
(V
= 1.0 or 9.0 Vdc)
O
ОООООООО
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
ОООООООО
ОООООООО
ОООООООО
(V
OH
(V
OH
(V
OH
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
ОООООООО
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance (Vin = 0)
Input Capacitance
MC14599B — Data (pin 3)
ОООООООО
= 0)
(V
in
Quiescent Current
ОООООООО
(Per Package)
ОООООООО
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
ОООООООО
Per Package)
(C
= 50 pF on all outputs, all
L
ОООООООО
buffers switching)
Symbol
ÎÎ
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
ÎÎ
I
OL
ÎÎ
I
in
C
in
C
in
ÎÎ
I
DD
ÎÎ
ÎÎ
I
T
ÎÎ
ÎÎ
DD
Vdc
Î
5.0
10
15
Î
5.0
10
Î
15
5.0
Î
10
Î
15
5.0
Î
10
Î
15
5.0
Î
5.0
Î
10
15
Î
5.0
10
Î
15
15
−
−
Î
5.0
Î
10
15
Î
5.0
10
Î
15
Î
Min
Î
Î
4.95
9.95
Î
14.95
Î
Î
3.5
Î
7.0
Î
11
– 3.0
Î
– 0.64
Î
– 1.6
– 4.2
Î
0.64
1.6
Î
4.2
Î
Î
Î
ООООООООООООООО
ООООООООООООООО
− 55C
−
−
−
−
−
−
−
−
−
−
−
−
SS
)
Max
Î
0.05
0.05
0.05
Î
Î
1.5
Î
3.0
Î
4.0
Î
Î
Î
Î
Î
Î
± 0.1
Î
5.0
Î
10
20
Î
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
25C
Min
ÎÎ
−
−
−
ÎÎ
4.95
9.95
ÎÎ
14.95
−
ÎÎ
−
ÎÎ
−
3.5
ÎÎ
7.0
ÎÎ
11
– 2.4
ÎÎ
– 0.51
ÎÎ
– 1.3
– 3.4
ÎÎ
0.51
1.3
ÎÎ
3.4
−
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
Typ
(Note 2)
Î
0
0
0
Î
5.0
10
Î
15
2.25
Î
4.50
Î
6.75
2.75
Î
5.50
Î
8.25
– 4.2
Î
– 0.88
Î
– 2.25
– 8.8
Î
0.88
2.25
Î
8.8
±0.00001
5.0
15
Î
0.005
Î
0.010
0.015
Î
IT = (1.5 A/kHz) f + I
IT = (3.0 A/kHz) f + I
IT = (4.5 A/kHz) f + I
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
−
−
ÎÎ
−
1.5
ÎÎ
3.0
ÎÎ
4.0
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
± 0.1
7.5
22.5
ÎÎ
5.0
ÎÎ
10
20
ÎÎ
DD
DD
DD
Min
Î
−
−
−
Î
4.95
9.95
Î
14.95
−
Î
−
Î
−
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
Î
– 0.9
– 2.4
Î
0.36
0.9
Î
2.4
−
−
−
Î
−
Î
−
−
Î
125C
Max
Î
0.05
0.05
0.05
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
150
Î
300
600
Î
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk
I
T(CL
where: I
is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
T
1.5
3.0
4.0
Unit
Î
Vdc
Î
−
Vdc
−
Î
−
Vdc
Î
Î
Vdc
−
Î
−
Î
−
mAdc
−
Î
−
Î
−
−
Î
−
mAdc
−
Î
−
Adc
−
−
pF
pF
Î
Adc
Î
Î
Adc
Î
Î
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3