ON Semiconductor MC14067B Technical data

MC14067B

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Analog Multiplexers / Demultiplexers

The MC14067 multiplexer/demultiplexer is a digitally controlled analog switch featuring low ON resistance and very low leakage current. This device can be used in either digital or analog applications.

The MC14067 is a 16−channel multiplexer/demultiplexer with an inhibit and four binary control inputs A, B, C, and D. These control inputs select 1−of−16 channels by turning ON the appropriate analog switch (see MC14067 truth table.)

Features

• Low OFF Leakage Current

• Matched Channel Resistance

• Low Quiescent Power Consumption

• Low Crosstalk Between Channels

• Wide Operating Voltage Range: 3 to 18 V

• Low Noise

• Pin for Pin Replacement for CD4067B

• Pb−Free Packages are Available*

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PDIP−24

P SUFFIX

CASE 709

SOIC−24 DW SUFFIX CASE 751E

MARKING

DIAGRAMS

MC14067BCP

AWLYYWW

14067B

AWLYYWW

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

ÎÎ

I

in

ÎÎ

I

sw

P

D

ÎÎ

T

A

T

stg

T

L

ÎÎ

DC Supply Voltage Range Input or Output Voltage Range

out

ООООООО

(DC or Transient) Input Current (DC or Transient),

per Control Pin

ООООООО

Switch Through Current Power Dissipation, per Package

ООООООО

(Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature

(8–Second Soldering)

ООООООО

Parameter

)

SS

Value

– 0.5 to + 18.0

– 0.5 to VDD + 0.5

ООООО

± 10

ООООО

± 25

ООООО

500

– 55 to + 125 – 65 to + 150

260

ООООО

Unit

V V

mA

mW

C C C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating: Plastic “P and D/DW” Packages: − 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V to the range V

 (Vin or V

SS

)  VDD.

out

and V

in

should be constrained

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

SS

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 5

1 Publication Order Number:

MC14067B/D

MC14067B

Selected

TRUTH TABLE

Control Inputs

A B C D Inh

X X X X 1 None

0 0 0 0 0 X0 1 0 0 0 0 X1 0 1 0 0 0 X2

1 1 0 0 0 X3 0 0 1 0 0 X4 1 0 1 0 0 X5 0 1 1 0 0 X6

1 1 1 0 0 X7 0 0 0 1 0 X8 1 0 0 1 0 X9 0 1 0 1 0 X10

1 1 0 1 0 X11 0 0 1 1 0 X12 1 0 1 1 0 X13 0 1 1 1 0 X14 1 1 1 1 0 X15

Channel

CONTROL

INPUTS

X

IN/OUT

PIN ASSIGNMENT 16−Channel Analog

1

X

2

X7

3

X6

4

X5

X4 X11

5

6

X3

7

X2

8

X1

9

X0

10

A

B

11

V

12

SS

FUNCTIONAL DIAGRAM

INHIBIT

A

X0 X1 X2 X3 X4 X5 X6 X7 X8

X9 X10 X11 X12 X13 X14 X15

B C D

1−OF−16 DECODER

V

24

DD

X8

23

X9

22

X10

21

20

X12

19

X13

18

17

X14

16

X15

15

INHIBIT

C

14

D

13

OUT/IN

CONTROLS

SWITCHES

IN/OUT

X

Multiplexer/Demultiplexer

INHIBIT

15

A

10

B

11

C

14

D

13

X0

9

X1

8

X2

7

X3

6

X4

5

X5

4

X6

3

X7

2

X8

23

X9

22

X10

21 20

X11 X12

19

X13

18

X14

17

X15

16

X

COMMON

1

OUT/IN

VDD = PIN 24 V

= PIN 12

SS

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2

MC14067B

Î

ELECTRICAL CHARACTERISTICS

− 55°C

Min

Max

Characteristic

Symbol

V

DD

Test Conditions

Min

SUPPLY REQUIREMENTS (Voltages Referenced to VSS)

Power Supply Voltage

V

DD

−

3.0

18

3.0

Range

Quiescent Current Per

ОООООО

Package

ОООООО

Total Supply Current

(Dynamic Plus

ОООООО

Quiescent,

ОООООО

Per Package

I

DD

Î

I

D(AV)

Î

5.0

Control Inputs: V

Î

ООООО

10

Switch I/O: V

15

ООООО

5.0

TA = 25C only (The

10

ООООО

15

ООООО

VSS or VDD,

in =

 V

SS

V V

DD

, and

switch

 500 mV

I/O

channel component, (V

– V

)/Ron, is

in

out

not included.)

−

Î



Î

(3)

Î

ООООООООООООО

5.0

Î

−

10

−

20

Î

Typical (0.20 A/kHz) f + I

CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)

Low−Level Input Voltage

ОООООО

High−Level Input Voltage

ОООООО

Input Leakage Current Input Capacitance

V

Î

V

Î

I

C

5.0 10

Î

15

5.0 10

Î

Ron = per spec, I

= per spec

off

ООООО

Ron = per spec, I

= per spec

off

ООООО

IL

IH

15 15 —

Vin = 0 or V

DD

in

Î

3.5

7.0

Î

−

1.5

−

3.0

Î

−

4.0

−

3.5

−

7.0

Î

11

−

± 0.1

−

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)

Recommended Peak−to−

ОООООО

Peak Voltage Into or Out of the Switch

ОООООО

Recommended Static or

Dynamic Voltage Across the Switch

ОООООО

V

I/O

Î

V

switch

(3)

Î

−

Channel On or Off

Î

−

Channel On

Î

ООООО

Î

0

V

DD

Î

0

600

Î

(Figure 1) Output Offset Voltage ON Resistance

ОООООО

V

R

Î

OO

on

−

Vin = 0 V, No Load

5.0

V

Î

10 15

Î

 500 mV

switch

ООООО

V

= VIL or V

in

(Control), and V

ООООО

(3)

IH

in

−

,

−

Î

800

Î

−

400

−

220

Î

0 to VDD (Switch)

ON Resistance

ОООООО

Between

Any Two Channels

ОООООО

R

Î

5.0

on

Î

ООООО

10 15

ООООО

Î

−

70

Î

−

50

−

45

Î

in the Same Package Off−Channel Leakage

ОООООО

Current (Figure 2)

ОООООО

Capacitance, Switch I/O

Capacitance, Common O/I

ОООООО

Capacitance, Feedthrough

(Channel Off)

I

Î

C C

Î

C

off

I/O O/I

I/O

15

Vin = VIL or V

Î

ООООО

(Control) Channel to Channel or Any One

ООООО

Channel

−

Inhibit = V

−

Inhibit = V

ООООО

(MC14067B) (MC14097B)

ООООО

DD DD

−−Pins Not Adjacent Pins Adjacent

−

IH

Î

± 100

Î

−

—

Î

−

Î

−

2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

3. For voltage drops across the switch (V the current out of the switch may contain both V

Maximum Ratings are exceeded. (See first page of this data sheet.)

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e.

switch

and switch input components. The reliability of the device will be unaffected unless the

DD

25C

(2)

Typ

−

0.005

Î

−

0.010

−

0.015

Î

(0.07 A/kHz) f + I

(0.36 A/kHz) f + I

−

2.25

−

4.50

Î

−

6.75

2.75

5.50

Î

11

Î

—

Î

−

0

−

Î

8.25

±0.00001

5.0

−

Î

−

Î

10

250

Î

120

80

Î

25

Î

10 10

Î

± 0.05

Î

10

Î

100

60

Î

0.47

Max

18

5.0

Î

10 20

Î

1.5

3.0

Î

4.0

Î

± 0.1

7.5

V

Î

600

Î

1050

Î

500 280

Î

70

Î

50 45

Î

±100

Î

−

DD

−

DD DD DD

Min

3.0

−

Î

−

Î

−

Î

−

3.5

7.0

Î

11

−

0

Î

0

Î

−

Î

−

Î

−

Î

−

Î

−

Î

−

Î

−

Î

−

125C

Max

18

150

Î

300 600

Î

1.5

3.0

Î

4.0

−

Î

−

1.0

−

V

DDVp−p

Î

300

Î

−

1300

Î

550 320

Î

135

Î

95 65

Î

±1000

Î

−

Î

−

Î

−

Unit

V

A

V

A pF

mV

V



nA

pF pF

pF

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3

MC14067B

Î

ELECTRICAL CHARACTERISTICS (C

= 50 pF, T

L

Characteristic

Propagation Delay Times

ОООООООООООООООО

Channel Input−to−Channel Output (R

MC14067B

ОООООООООООООООО

= 200 k)

L

Control Input−to−Channel Output Channel Turn−On Time (R

ОООООООООООООООО

MC14067B

ОООООООООООООООО

= 10 k)

L

Channel Turn−Off Time (RL = 300 k)

MC14067B

ОООООООООООООООО

Any Pair of Address Inputs to Output

ОООООООООООООООО

MC14067B

ОООООООООООООООО

Second Harmonic Distortion

(R

= 10 k, f = 1 kHz, Vin = 5 V

L

ОООООООООООООООО

p−p

)

ON Channel Bandwidth

[R

= 1 k, Vin = 1/2 (VDD – VSS)

L

ОООООООООООООООО

20 Log10 (V

) = − 3 dB MC14067B

out/Vin

(sine−wave)]

p−p

Off Channel Feedthrough Attenuation

[R

= 1 k, Vin = 1/2 (VDD−VSS)

L

ОООООООООООООООО

(sine−wave)]

p−p

f

= 20 MHz – MC14067B

in

Channel Separation

ОООООООООООООООО

[R

= 1 k, Vin = 1/2 (VDD−VSS)

L

ОООООООООООООООО

(sine−wave)]

p−p

Crosstalk, Control Inputs−to−Common O/I

(R1 = 1 k, R

ОООООООООООООООО

Control t

= 10 k,

L

= tf = 20 ns, Inhibit = VSS)

r

= 25C)

A

f

= 20 MHz

in

Symbol

t

PLH,tPHL

ÎÎÎ

(Figure 3)

ÎÎÎ

t

, t

PZH

PZL

ÎÎÎ

(Figure 4)

ÎÎÎ

t

PHZ,tPLZ

ÎÎÎ

(Figure 4)

ÎÎÎ

t

, t

PLH

PHL

ÎÎÎ

−

ÎÎÎ

BW

ÎÎÎ

(Figure 5)

−

ÎÎÎ

(Figure 5)

−

ÎÎÎ

(Figure 6)

ÎÎÎ

−

ÎÎÎ

(Figure 7)

VDD – V

Vdc

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15 10

ÎÎ

10 10

ÎÎ

10

ÎÎ

10

ÎÎ

SS

(4)

Typ

ÎÎ

35

ÎÎ

15

ÎÎ

12

ÎÎ

240

ÎÎ

115

75

ÎÎ

250 120

ÎÎ

75

ÎÎ

280

ÎÎ

115

ÎÎ

85

0.3

ÎÎ

15

– 40

ÎÎ

– 40

ÎÎ

30

ÎÎ

Max

ÎÎ

90

ÎÎ

40

ÎÎ

30

ÎÎ

600

ÎÎ

290 190

ÎÎ

625 300

ÎÎ

190

ÎÎ

700

ÎÎ

290

ÎÎ

215

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

ns

Î

ns

Î

ns

Î

ns

Î

%

Î

MHz

Î

dB

Î

dB

Î

mV

Î

ORDERING INFORMATION

Device Package Shipping

MC14067BCP PDIP−14 500 Units / Rail MC14067BCPG PDIP−14

500 Units / Rail

(Pb−Free) MC14067BDW SOIC−14 55 Units / Rail MC14067BDWG SOIC−14

55 Units / Rail

(Pb−Free) MC14067BDWR2 SOIC−14 2500 Units / Tape & Reel MC14067BDWR2G SOIC−14

2500 Units / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

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4

†

MC14067B

ON SWITCH

CONTROL

SECTION

OF IC

CONTROL

SECTION

OF IC

LOAD

V

SOURCE

Figure 1. V Across Switch Figure 2. Off Channel Leakage

V

C

A B C D

INH

20 ns 20 ns

t

, t

PZH

PZL

V

DD

A B

C D

INH

20 ns 20 ns

V

in

t

PLH

V

out

PULSE

GENERATOR

V

out

R

L

V

in

90%

50%

t

PHL

CL = 50 pF

10%

50%

V

C

V

DD

V

SS

V

out

V

out

50%

OFF CHANNEL UNDER TEST

A

OTHER CHANNEL(S)

V

X

DD

CL = 50 pF

R

L

V

in

VDDVSSVSSV

90% 50%

10%

90%

t

, t

PHZ

PLZ

10%

V

DD

V

SS

V

SS

V

DD

V

SS

V

DD

out

Vin = V VX = V

DD

SS

DD

Figure 3. Propagation Delay Test Circuit

and Waveforms V

in

to V

out

Figure 4. T urn−On and Delay Turn−Off

Test Circuit and Waveforms

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5

A, B, and C inputs used to turn ON or OFF the switch under test.

A B C D

INH

R

L

V

out

CL = 50 pF

MC14067B

V

DD

A B

ON C D

OFF

INH

R

L

V

out

R

L

CL = 50 pF

V

in

Figure 5. Bandwidth and Off−Channel

Feedthrough Attenuation

V

C

Figure 7. Crosstalk, Control to Common O/I

A B C D

INH

R1

V

in

Figure 6. Channel Separation

(Adjacent Channels Used for Setup)

V

out

R

L

CL = 50 pF

V

A

V

B

A B C D

INH

V

DD

V

DD

KEITHLEY 160

DIGITAL

MULTIMETER

10 k

V

DD

1 k

RANGE

V

SS

Figure 8. Channel Resistance (RON) Test Circuit

X−Y

PLOTTER

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6

C

L

V

out

V

A

V

B

t

PHL

V

out

50%

t

50%

Figure 9. Propagation Delay, Any Pair of

Address Inputs to Output

PLH

MC14067B

TYPICAL RESISTANCE CHARACTERISTICS

350

300

250

200

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

700

600

500

400

350

300

250

200

V

, INPUT VOLTAGE (VOLTS)

in

T

= 125°C

A

25°C

−55 °C

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

T

= 125°C

A

25°C

−55 °C

Figure 10. VDD = 7.5 V, VSS = − 7.5 V Figure 11. VDD = 5.0 V, VSS = − 5.0 V

350

T

= 25°C

300

250

200

A

VDD = 2.5 V

300

200

, ON" RESISTANCE (OHMS)

ON

R

100

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

T

= 125°C

A

25°C

−55 °C

V

, INPUT VOLTAGE (VOLTS)

in

Figure 12. VDD = 2.5 V, VSS = − 2.5 V

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

Figure 13. Comparison at 25°C, VDD = − V

5.0 V

7.5 V

Vin, INPUT VOLTAGE (VOLTS)

SS

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MC14067B

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Multiplexer / Demultiplexer. The 0−to−5 V Digital Control signal is used to directly control a 5 V

The digital control logic levels are determined by V and VSS. The VDD voltage is the logic high voltage; the V

analog signal.

p−p

DD

SS

voltage is logic low . For the example. VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VSS. The analog voltage must swing neither higher than VDD nor lower than VSS. The example shows a 5 V

+5 V

V

DD

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

5 V

p−p

ANALOG SIGNAL

0−TO−5 V DIGITAL

CONTROL SIGNALS

SWITCH

I/O

p−p

MC14067B

signal which allows no margin at either peak. If voltage transients above VDD and/or below VSS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping.

The absolute maximum potential difference between V and VSS is 18.0 volts. Most parameters are specified up to 15 V which is the recommended maximum difference between V

V

SS

COMMON

O/I

and VSS.

DD

5 V

p−p

ANALOG SIGNAL

DD

+5.0 V

+2.5 V

GND

Figure A. Application Example

V

DD

D

X

SWITCH

I/O

D

X

V

SS

COMMON

O/I

V

DD

D

X

D

X

V

SS

Figure B. External Germanium or Schottky Clipping Diodes

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MC14067B

PACKAGE DIMENSIONS

PDIP−24

P SUFFIX

CASE 709−02

ISSUE C

−T−

SEATING PLANE

1324

B

112

A

N

C

K

H

G

F

D

SEATING PLANE

−A−

1324

−B− P12X

1

12

D24X

0.010 (0.25) B

M

S

A

T

S

G22X

J

L

M

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

4. CONTROLLING DIMENSION: INCH.

DIM MIN MAX MIN MAX

A 31.37 32.131.235 1.265 B 13.72 14.220.540 0.560 C 3.94 5.080.155 0.200 D 0.36 0.560.014 0.022 F 1.02 1.520.040 0.060 G 2.54 BSC0.100 BSC H 1.65 2.030.065 0.080

J 0.20 0.380.008 0.015 K 2.92 3.430.115 0.135 L 15.24 BSC0.600 BSC M 0 15 0 15

 

N 0.51 1.020.020 0.040

MILLIMETERSINCHES

SOIC−24

DW SUFFIX

CASE 751E−04

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

M

0.010 (0.25) B

M

J

F

R

X 45



C

M

K

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 15.25 15.54 0.601 0.612 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.41 0.90 0.016 0.035 G 1.27 BSC 0.050 BSC

J 0.23 0.32 0.009 0.013 K 0.13 0.29 0.005 0.011 M 0 8 0 8 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS



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9

MC14067B

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

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MC14067B/D

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ON Semiconductor MC14067B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual