ON Semiconductor MC14051B, MC14052B, MC14053B Technical data

MC14051B, MC14052B, MC14053B

Analog Multiplexers/Demultiplexers

The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally−controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.

Features

• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Analog Voltage Range (V

Note: VEE must be  V

• Linearized Transfer Characteristics

• Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical

• Pin−for−Pin Replacement for CD4051, CD4052, and CD4053

• For 4PDT Switch, See MC14551B

• For Lower R

CMOS Devices

, Use the HC4051, HC4052, or HC4053 High−Speed

ON

• Pb−Free Packages are Available*

− VEE) = 3.0 to 18 V

DD

SS

http://onsemi.com

PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16 DT SUFFIX

CASE 948F

16

1

16

MARKING

DIAGRAMS

MC140xxBCP

AWLYYWW

140xxB

AWLYWW

1

16

14

0xxB

ALYW

1

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

Vin,

V

I

T

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/C From

65C To 12 5C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V the range V

Unused inputs must always be tied to a n appropriate l ogic voltage l evel ( e.g., either V

SS

DC Supply Voltage Range

DD

out

I

in

SW

P

D

T

A

stg

T

L

, VEE or VDD). Unused outputs must be left open.

(Referenced to V

Input or Output Voltage Range

(DC or Transient) (Referenced to V

Control Inputs and V Input Current (DC or Transient) per Control Pin +10 mA Switch Through Current ±25 mA Power Dissipation per Package (Note 1) 500 mW Ambient Temperature Range −55 to +125 °C Storage Temperature Range −65 to +150 °C Lead Temperature (8−Second Soldering) 260 °C

 (Vin or V

SS

)  VDD.

out

, VSS ≥ VEE)

EE

for Switch I/O)

EE

in

SS

and V

)

SS

−0.5 to +18.0

−0.5 to V

for

should be constrained to

out

DD

+ 0.5

V

16

SOEIAJ−16

F SUFFIX

CASE 966

xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

MC140xxB

AWLYWW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 6

1 Publication Order Number:

MC14051B/D

MC14051B, MC14052B, MC14053B

MC14051B

8−Channel Analog

Multiplexer/Demultiplexer

INHIBIT

6

A

CONTROLS

SWITCHES

IN/OUT

11

10

9 13 14 15 12

1

5

2

4

B C X0 X1 X2 X3 X4 X5 X6 X7

VDD = PIN 16

V

= PIN 8

SS

V

= PIN 7

EE

X

3

COMMON

OUT/IN

Multiplexer/Demultiplexer

CONTROLS

SWITCHES

IN/OUT

MC14052B

Dual 4−Channel Analog

INHIBIT

6

A

10

9 12 14 15 11

1

5

2

4

B X0

X1 X2 X3 Y0 Y1 Y2

Y3

V

DD

V

SS

V

EE

X

Y

= PIN 16

= PIN 8 = PIN 7

13

3

COMMONS

OUT/IN

Triple 2−Channel Analog

Multiplexer/Demultiplexer

CONTROLS

SWITCHES

IN/OUT

Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

PIN ASSIGMENT

MC14051B MC14052B MC14053B

V

16

DD

X2

15

X1

14

X0

13

X3

125

A

11

B

10

C

9

INH

V

Y0

Y2

Y3

Y1

1

2

3

Y

4

6

7

EE

8

SS

V

16

DD

X2

15

X1

14

X

13

X0

125

11

X3

10

A

9

B

INH

V

X4

X6

X7

X5

1

2

X

3

4

6

7

EE

8

SS

MC14053B

INHIBIT

6

A

11

B

10

C

9

X0

12

X1

13

Y0

2

Y1

1

Z0

5

Z1

3

V

= PIN 16

DD

V

SS

V

EE

1

Y1

2

Y0

3

Z1

4

Z

Z0

INH

6

7

V

EE

8

V

SS

= PIN 8 = PIN 7

14

X

COMMONS

15

Y

Z

16

15

14

13

125

10

OUT/IN

4

V

DD

Y

X

X1

X0

11

A

B

9

C

http://onsemi.com

2

MC14051B, MC14052B, MC14053B

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

Î ÎÎ ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

Î ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

Î ÎÎ

Î

ÎÎ

Î

ÎÎ

ELECTRICAL CHARACTERISTICS

− 55C

Characteristic

ОООООО

Symbol

Î

V

Î

DD

Test Conditions

ОООООО

Min

Max

Î

Min

Î

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

ОООООО

Range

Quiescent Current Per

Package

ОООООО

Total Supply Current

(Dynamic Plus

ОООООО

Quiescent, Per Package

ОООООО

V

Î

I

DD

Î

I

D(AV)

Î

DD

−

VDD – 3.0 ≥ V

Î

ОООООО

5.0

Control Inputs:

10

V

ОООООО

in

15

Switch I/O: V

ОООООО

V

DD

500 mV (Note 3)

ОООООО

5.0

TA = 25C only (The

10

channel component,

ОООООО

15

(V not included.)

ОООООО

SS

= VSS or VDD,

EE

, and V

– V

in

)/Ron, is

out

switch

≥ V

 V



EE

I/O



3.0

18

5.0 10 20

3.0

Î

−

Î

−

Î

Typical (0.20 A/kHz) f + I

ОООООООООООО

CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

Low−Level Input Voltage

ОООООО

High−Level Input Voltage

ОООООО

Input Leakage Current Input Capacitance

V

Î

V

Î

I

C

5.0 10

Î

15

5.0 10

Î

15 15

−

Ron = per spec,

= per spec

I

off

ОООООО

Ron = per spec, I

= per spec

off

ОООООО

Vin = 0 or V

DD

IL

IH

in

3.5

7.0 11

−

1.5

−

3.0

Î

−

Î

−

4.0

−

± 0.1

−

Î

3.5

7.0

Î

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)

Recommended

Peak−to−Peak Voltage

ОООООО

V

Î

I/O

−

Channel On or Off

Î

ОООООО

0

V

DD

Î

Into or Out of the Switch

Recommended Static or

ОООООО

Dynamic Voltage Across the Switch (Note 3)

ОООООО

V

Î

switch

Î

−

Channel On

ОООООО

0

600

Î

(Figure 5) Output Offset Voltage ON Resistance

ОООООО

ON Resistance Between

ОООООО

Any Two Channels in the

Same Package

ОООООО

Off−Channel Leakage

Current (Figure 10)

ОООООО

Capacitance, Switch I/O Capacitance, Common O/I

ОООООО

Capacitance, Feedthrough

(Channel Off)

V

R

Î

R

Î

I

Î

C C

Î

C

OO

on

off

I/O O/I

I/O

−

Vin = 0 V, No Load

5.0

V

Î

10 15

Î

5.0

on

Î

10 15

Î

15

Vin = VIL or V

Î

−

Inhibit = V

−

Inhibit = V

Î

−−Pins Not Adjacent Pins Adjacent

 500 mV

switch

ОООООО

(Note 3) V (Control), and Vin =

ОООООО

0 to V

ОООООО

(Switch)

DD

= VIL or V

in

IH

(Control) Channel to

ОООООО

Channel or Any One Channel

ОООООО

DD DD

(MC14051B)

ОООООО

(MC14052B) (MC14053B)

ОООООО

−

800

Î

−

Î

−

Î

−

Î

−

± 100

Î

−

Î

−

Î

−

400 220

70 50 45

−

Î

2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.

3. For voltage drops across the switch (V current out of the switch may contain both V Maximum Ratings are exceeded. (See first page of this data sheet.)

) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the

switch

and switch input components. The reliability of the device will be unaffected unless the

DD

25C

Typ

(Note 2)

ÎÎ

−

ÎÎ

−

0.005

−

0.010

ÎÎ

−

0.015

ÎÎ

(0.07 A/kHz) f + I

(0.36 A/kHz) f + I

−

2.25

−

4.50

ÎÎ

−

6.75

2.75

5.50

ÎÎ

11

8.25

−

±0.00001

−

0

−

5.0

−

ÎÎ

−

ÎÎ

10

250

ÎÎ

120

80

ÎÎ

25

ÎÎ

10 10

ÎÎ

± 0.05

ÎÎ

10

60

ÎÎ

32 17

ÎÎ

0.15

0.47

Max

Î

± 0.1

V

Î

600

Î

1050

Î

500 280

Î

± 100

Î

18

5.0 10 20

1.5

3.0

4.0

7.5

70 50 45

−

DD

−

DD DD DD

Min

Î

3.0

Î

3.5

7.0

Î

11

Î

125C

−

0

−

Max

Î

18

Î

150 300

Î

600

Î

1.5

3.0

Î

4.0

−

Î

−

1.0

−

V

DDVPP

Î

300

Î

−

1200

Î

520 300

Î

135

Î

95 65

Î

±1000

Î

−

Î

−

Î

−

Unit

V

A

V

A pF

mV

V



nA

pF pF

pF

http://onsemi.com

3

MC14051B, MC14052B, MC14053B

Î

ELECTRICAL CHARACTERISTICS (Note 4) (C

Characteristic

Propagation Delay Times (Figure 6)

ООООООООООООО

Switch Input to Switch Output (R

MC14051

ООООООООООООО

t

PLH

t

PLH

t

PLH

, t

= (0.17 ns/pF) CL + 26.5 ns

PHL

, t

= (0.08 ns/pF) CL + 11 ns

PHL

, t

= (0.06 ns/pF) CL + 9.0 ns

PHL

= 10 k)

L

= 50 pF, TA = 25C) (VEE  VSS unless otherwise indicated)

L

Symbol

t

, t

PLH

ÎÎÎ

PHL

VDD – V

EE

Vdc

ÎÎÎÎ

5.0 10

ÎÎÎÎ

15

Typ (Note 5)

All Types

ÎÎÎ

35 15

ÎÎÎ

12

Max

ÎÎ

90 40

ÎÎ

30

MC14052

ООООООООООООО

t

PLH

t

PLH

t

PLH

, t

= (0.17 ns/pF) CL + 21.5 ns

PHL

, t

= (0.08 ns/pF) CL + 8.0 ns

PHL

, t

= (0.06 ns/pF) CL + 7.0 ns

PHL

ÎÎÎ

ÎÎÎÎ

5.0 10

ÎÎÎÎ

15

ÎÎÎ

30 12

ÎÎÎ

10

ÎÎ

75 30

ÎÎ

25

MC14053

t

, t

ООООООООООООО

PLH

t

PLH

t

PLH

= (0.17 ns/pF) CL + 16.5 ns

PHL

, t

= (0.08 ns/pF) CL + 4.0 ns

PHL

, t

= (0.06 ns/pF) CL + 3.0 ns

PHL

Inhibit to Output (RL = 10 k, VEE = VSS) Output “1” or “0” to High Impedance, or

ООООООООООООО

High Impedance to “1” or “0” Level

MC14051B

ООООООООООООО

MC14052B

ООООООООООООО

MC14053B

ООООООООООООО

Control Input to Output (RL = 10 k, VEE = VSS)

ООООООООООООО

MC14051B

ООООООООООООО

MC14052B

ООООООООООООО

MC14053B

ООООООООООООО

Second Harmonic Distortion

(R

= 10K, f = 1 kHz) Vin = 5 V

L

PP

Bandwidth (Figure 7)

= 1 k, Vin = 1/2 (VDD−VEE) p−p, CL = 50pF

(R

ООООООООООООО

L

20 Log (V

out/Vin

) = − 3 dB)

Off Channel Feedthrough Attenuation (Figure 7)

ООООООООООООО

R

= 1K, Vin = 1/2 (VDD − VEE) p−p

L

= 4.5 MHz — MC14051B

f

in

ООООООООООООО

= 30 MHz — MC14052B

f

in

ООООООООООООО

f

= 55 MHz — MC14053B

in

Channel Separation (Figure 8)

(R

= 1 k, Vin = 1/2 (VDD−VEE) p−p,

L

ООООООООООООО

= 3.0 MHz

f

in

Crosstalk, Control Input to Common O/I (Figure 9)

= 1 k, RL = 10 k

(R

1

ООООООООООООО

Control t

TLH

= t

= 20 ns, Inhibit = VSS)

THL

ÎÎÎ

t

, t

PHZ

t

PZH

ÎÎÎ

ÎÎÎÎÎÎÎÎ

t

PLH

ÎÎÎ

,

PLZ

, t

PZL

, t

PHL

−

BW

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

10

ÎÎÎÎ

15

ÎÎÎÎ

5.0

ÎÎÎÎ

10

ÎÎÎÎ

15

5.0 10 15

ÎÎÎÎ

5.0 10

ÎÎÎÎ

15

5.0

ÎÎÎÎ

10 15

ÎÎÎÎ

5.0

ÎÎÎÎ

10 15

ÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎ

25

ÎÎÎ

8.0

ÎÎÎ

6.0

ÎÎÎ

350

ÎÎÎ

170

ÎÎÎ

140 300

155

ÎÎÎ

125 275

140

ÎÎÎ

110

ÎÎÎ

360 160

ÎÎÎ

120 325

ÎÎÎ

130

90

ÎÎÎ

300

ÎÎÎ

120

80

ÎÎÎ

0.07

17

ÎÎÎ

– 50

ÎÎÎ

– 50

ÎÎÎ

75

ÎÎÎ

65

ÎÎ

20

ÎÎ

15

ÎÎ

700

ÎÎ

340

ÎÎ

280 600

310

ÎÎ

250 550

280

ÎÎ

220

ÎÎ

720 320

ÎÎ

240 650

ÎÎ

260 180

ÎÎ

600

ÎÎ

240 160

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

4. The formulas given are for the typical characteristics only at 25C.

5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.

Unit

Î

MHz

Î

dB

Î

dB

Î

mV

Î

ns

%

http://onsemi.com

4

IN/OUT

LEVEL CONVERTED CONTROL

MC14051B, MC14052B, MC14053B

V

DD

V

DD

V

DD

V

EE

IN/OUT OUT/IN

OUT/IN

V

EE

Figure 1. Switch Circuit Schematic

TRUTH TABLE

Control Inputs

Select

Inhibit

C* B A MC14051B MC14052B MC14053B

0 0 0 0 X0 Y0 X0 Z0 Y0 X0 0 0 01 X1 Y1 X1 Z0 Y0 X1 0 0 10 X2 Y2 X2 Z0 Y1 X0 0 0 11 X3 Y3 X3 Z0 Y1 X1

0 1 0 0 X4 Z1 Y0 X0 0 1 01 X5 Z1 Y0 X1 0 1 10 X6 Z1 Y1 X0 0 1 11 X7 Z1 Y1 X1

1 x x x None None None

*Not applicable for MC14052 x = Don’t Care

16 V

DD

INH6

A10

LEVEL

CONVERTER

B9

X012

8VSS7V

EE

X114

X215

X311

Y01 Y15

Y22 Y34

ON Switches

BINARY TO 1−OF−4

DECODER WITH

INHIBIT

13X

3Y

CONTROL

16 V

DD

INH6

A11 B10 C9

X013

LEVEL

CONVERTER

8V

SS

7V

BINARY TO 1−OF−8

DECODER WITH

INHIBIT

EE

X114

X215 X312

X41 X55

X62 X74

Figure 2. MC14051B Functional Diagram

16 V

DD

INH6

A11 B10

C9

X012

X113 Y02

Y11 Z05

Z13

LEVEL

CONVERTER

8VSS7V

BINARY TO 1−OF−2

DECODER WITH

INHIBIT

EE

3X

14X

15Y

4Z

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

http://onsemi.com

5

CONTROL

SECTION

OF IC

SOURCE

ON SWITCH

V

MC14051B, MC14052B, MC14053B

TEST CIRCUITS

GENERATOR

LOAD

PULSE

A B C

INH

V

out

R

C

L

VDDVEEVEEV

Figure 5. V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output

A, B, and C inputs used to turn ON or OFF the switch under test.

A B C

V

VDD − V

2

SS

EE

INH

R

L

V

in

CL = 50 pF

Figure 7. Bandwidth and Off−Channel

Feedthrough Attenuation

V

out

VDD − V

EE

2

(Adjacent Channels Used For Setup)

A B

ON

C

OFF

INH

V

in

Figure 8. Channel Separation

DD

R

L

V

out

R

CL = 50 pF

L

A B

C

INH

R

L

R1

V

out

CL = 50 pF

Figure 9. Crosstalk, Control Input to

Common O/I

NOTE: See also Figures 7 and 8 in the MC14016B data sheet.

http://onsemi.com

OFF CHANNEL UNDER TEST

V

DD

V

CONTROL

SECTION

OF IC

OTHER CHANNEL(S)

COMMON

EE

V

EE

V

DD

V

EE

V

DD

Figure 10. Off Channel Leakage

6

350

10 k

VEE = V

MC14051B, MC14052B, MC14053B

V

DD

V

DD

SS

Figure 11. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

KEITHLEY 160

DIGITAL

MULTIMETER

1 k

RANGE

350

X−Y

PLOTTER

300

250

200

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

700

600

500

400

300

200

, ON" RESISTANCE (OHMS)

ON

R

100

V

, INPUT VOLTAGE (VOLTS)

in

Figure 12. V

300

250

200

T

= 125°C

A

25°C

−55 °C

= 7.5 V, VEE = − 7.5 V Figure 13. VDD = 5.0 V, VEE = − 5.0 V

DD

150

100

, ON" RESISTANCE (OHMS)

ON

R

50

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

350

T

= 25°C

300

250

A

VDD = 2.5 V

200

150

T

= 125°C

A

25°C

−55 °C

100

, ON" RESISTANCE (OHMS)

ON

R

50

5.0 V

T

= 125°C

A

25°C

−55 °C

7.5 V

0

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

Figure 14. VDD = 2.5 V, VEE = − 2.5 V

0

http://onsemi.com

7

−8.0−10 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 10

V

, INPUT VOLTAGE (VOLTS)

in

Figure 15. Comparison at 25°C, VDD = − V

EE

MC14051B, MC14052B, MC14053B

Î

ÎÎÎÎ

Î

ÎÎÎÎ

APPLICATIONS INFORMATION

Figure A illustrates use of the on−chip level converter detailed in Figures 2, 3, and 4. The 0−to−5 V Digital Control signal is used to directly control a 9 V

The digital control logic levels are determined by V and VSS. The VDD voltage is the logic high voltage; the V

analog signal.

p−p

DD

SS

voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by V

DD

and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD − VSS = 5 V maximum swing above VSS; VSS − VEE = 5 V maximum swing below VSS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each

+5 V −5 V

+5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

9 V

p−p

ANALOG SIGNAL

0−TO−5 V DIGITAL

CONTROL SIGNALS

V

DD

SWITCH

I/O

INHIBIT,

A, B, C

V

SS

MC14051B MC14052B MC14053B

peak. If voltage transients above V

and/or below VEE are

DD

anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping.

The absolute maximum potential difference between

V

and VEE is 18.0 V. Most parameters are specified up t o

DD

15 V which is the recommended maximum difference between V

and VEE.

DD

Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5 V, and VEE – 3 V is acceptable. See the T able below.

V

EE

COMMON

O/I

9 V

p−p

ANALOG SIGNAL

+4.5 V

GND

−4.5 V

Figure A. Application Example

V

DD

D

X

ANALOG

I/O

D

X

V

EE

Figure B. External Germanium or Schottky Clipping Diodes

POSSIBLE SUPPLY CONNECTIONS

ÎÎ

V

In Volts

ÎÎ

+ 8 + 5 + 5 + 5

+ 10

DD

ÎÎÎ

V

SS

In Volts

ÎÎÎ

0 0 0 0

+ 5

ÎÎ

V

EE

In Volts

ÎÎ

– 8

– 12

0 – 5 – 5

COMMON

O/I

Control Inputs

ООООО

Logic High/Logic Low

In Volts

ООООО

+ 8/0 + 5/0 + 5/0 + 5/0

+ 10/ + 5

V

DD

D

X

D

X

V

EE

ООООООО

Maximum Analog Signal Range

ООООООО

In Volts

+ 8 to – 8 = 16 V

+ 5 to – 12 = 17 V

+ 5 to 0 = 5 V

+ 5 to – 5 = 10 V

+ 10 to – 5 = 15 V

p–p

http://onsemi.com

8

MC14051B, MC14052B, MC14053B

ORDERING INFORMATION

Device Package Shipping

MC14051BCP PDIP−16 500 Units / Rail MC14051BCPG PDIP−16

(Pb−Free) MC14051BD SOIC−16 48 Units / Rail MC14051BDG SOIC−16

(Pb−Free) MC14051BDR2 SOIC−16 2500 / Tape & Reel MC14051BDR2G SOIC−16

(Pb−Free) MC14051BDTR2 TSSOP−16* 2500 / Tape & Reel MC14051BF SOEIAJ−16 50 Units / Rail MC14051BFEL SOEIAJ−16 2000 / Tape & Reel MC14051BFELG SOEIAJ−16

(Pb−Free)

MC14052BCP PDIP−16 500 Units / Rail MC1405BCPG PDIP−16

(Pb−Free) MC14052BD SOIC−16 48 Units / Rail MC14052BDG SOIC−16

(Pb−Free) MC14052BDR2 SOIC−16 2500 / Tape & Reel MC14052BDR2G SOIC−16

(Pb−Free) MC14052BDTR2 TSSOP−16* 2500 / Tape & Reel MC14052BF SOEIAJ−16 50 Units / Rail MC14052BFEL SOEIAJ−16 2000 / Tape & Reel MC14052BFELG SOEIAJ−16

(Pb−Free)

500 Units / Rail

48 Units / Rail

2500 / Tape & Reel

2000 / Tape & Reel

500 Units / Rail

48 Units / Rail

2500 / Tape & Reel

2000 / Tape & Reel

†

MC14053BCP PDIP−16 500 Units / Rail MC14053BCPG PDIP−16

(Pb−Free) MC14053BD SOIC−16 48 Units / Rail MC14053BDG SOIC−16

(Pb−Free) MC14053BDR2 SOIC−16 2500 / Tape & Reel MC14053BDR2G SOIC−16

(Pb−Free) MC14053BDTR2 TSSOP−16* 2500 / Tape & Reel MC14053BF SOEIAJ−16 50 Units / Rail MC14053BFG SOEIAJ−16

(Pb−Free) MC14053BFEL SOEIAJ−16 2000 / Tape & Reel MC14053BFELG SOEIAJ−16

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

500 Units / Rail

48 Units / Rail

2500 / Tape & Reel

50 Units / Rail

2000 / Tape & Reel

http://onsemi.com

9

MC14051B, MC14052B, MC14053B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

−A−

916

B

18

F

C

S

−T−

H

G

D

16 PL

0.25 (0.010) T

K

M

A

L

SEATING PLANE

J

M

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77

M

G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

M

S

X 45

R



F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7



P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

http://onsemi.com

10

MC14051B, MC14052B, MC14053B

ÉÉ

PACKAGE DIMENSIONS

TSSOP−16 DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F−01

ISSUE A

0.10 (0.004)

−T−

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

16X REFK

0.10 (0.004) V

M

S

U

T

S

K

K1

16

9

J1

B

−U−

1

8

J

N

A

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

DETAIL E

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

−W−

L 6.40 BSC 0.252 BSC M 0 8 0 8



INCHESMILLIMETERS

G

http://onsemi.com

11

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

MC14051B, MC14052B, MC14053B

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE O

L

E

Q

1

H

E

A

1

0.10 (0.004)

VIEW P

M



L

DETAIL P

c

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

INCHES

10



10

0



ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA

Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center

2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051

Phone: 81−3−5773−3850

http://onsemi.com

ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder

For additional information, please contact your local Sales Representative.

MC14051B/D

12

ON Semiconductor MC14051B, MC14052B, MC14053B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual