
MC14040B
12−Bit Binary Counter
The MC14040B 12−stage binary counter is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple−carry binary counter. The device
advances the count on the negative−going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency−driving circuits.
Features
• Fully Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Common Reset Line
• Pin−for−Pin Replacement for CD4040B
• Pb−Free Packages are Available*
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PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
16
1
16
MARKING
DIAGRAMS
MC14040BCP
AWLYYWW
14040B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
Vin, V
Iin, I
P
T
T
T
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation, per Package
D
Ambient Temperature Range −55 to +125 °C
A
Storage Temperature Range −65 to +150 °C
stg
Lead Temperature
L
SS
SS
Parameter Value Unit
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
(Vin or V
or VDD). Unused outputs must be left open.
) VDD.
out
)
SS
−0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
and V
in
should be constrained
out
16
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
14
040B
ALYW
1
16
MC14040B
AWLYWW
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 6
1 Publication Order Number:
MC14040B/D

PIN ASSIGNMENT
MC14040B
RESET
CLOCK
11
Q12
Q6
Q5
Q7
Q4
Q3
Q2
V
1
2
3
4
6
7
8
SS
V
16
DD
Q11
15
Q10
14
Q8
13
Q9
125
11
R
10
C
9
Q1
Clock Reset Output State
X 1 All Outputs are low
X = Don’t Care
TRUTH TABLE
0 No Change
0 Advance to next state
LOGIC DIAGRAM
Q1 Q2 Q3 Q10 Q11 Q12
976 14151
10
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
CQ
R
CQ
C
R
Q4 = PIN 5
Q5 = PIN 3
Q6 = PIN 2
Q7 = PIN 4
Q8 = PIN 13
Q9 = PIN 12
V
DD
V
SS
= PIN 16
= PIN 8
ORDERING INFORMATION
Device Package Shipping
MC14040BCP PDIP−16 500 Units / Rail
MC14040BCPG PDIP−16
(Pb−Free)
MC14040BD SOIC−16 48 Units / Rail
MC14040BDG SOIC−16
(Pb−Free)
MC14040BDR2 SOIC−16 2500 Units / Tape & Reel
MC14040BDR2G SOIC−16
(Pb−Free)
MC14040BDT TSSOP−16* 96 Units / Rail
MC14040BDTR2 TSSOP−16* 2500 Units / Tape & Reel
MC14040BFEL SOEIAJ−16 2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
500 Units / Rail
48 Units / Rail
2500 Units / Tape & Reel
†
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2

MC14040B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
Characteristic
ОООООООО
Output Voltage “0” Level
V
= VDD or 0
in
ОООООООО
“1” Level
V
= 0 or V
in
ОООООООО
DD
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
ОООООООО
O
= 9.0 or 1.0 Vdc)
(V
O
ОООООООО
= 13.5 or 1.5 Vdc)
(V
O
“1” Level
= 0.5 or 4.5 Vdc)
(V
ОООООООО
O
(V
= 1.0 or 9.0 Vdc)
O
ОООООООО
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
ОООООООО
ОООООООО
ОООООООО
(V
OH
(V
OH
(V
OH
= 4.6 Vdc)
= 9.5 Vdc)
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
ОООООООО
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
= 0)
in
ОООООООО
Quiescent Current
(Per Package)
ОООООООО
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
ОООООООО
Per Package)
ОООООООО
(C
= 50 pF on all outputs, all
L
buffers switching)
ОООООООО
Symbol
ÎÎ
V
OL
ÎÎ
V
OH
ÎÎ
V
IL
ÎÎ
ÎÎ
V
IH
ÎÎ
ÎÎ
I
OH
ÎÎ
ÎÎ
ÎÎ
I
OL
ÎÎ
I
in
C
in
ÎÎ
I
DD
ÎÎ
I
T
ÎÎ
ÎÎ
ÎÎ
DD
Vdc
Î
5.0
10
15
Î
5.0
10
Î
15
5.0
Î
10
Î
15
5.0
Î
10
Î
15
5.0
Î
5.0
Î
10
15
Î
5.0
10
Î
15
15
−
Î
5.0
10
Î
15
5.0
10
Î
15
Î
Î
Min
Î
Î
4.95
9.95
Î
14.95
Î
Î
3.5
Î
7.0
Î
11
– 3.0
Î
– 0.64
Î
– 1.6
– 4.2
Î
0.64
1.6
Î
4.2
Î
Î
ООООООООООООООО
ООООООООООООООО
ООООООООООООООО
− 55C
−
−
−
−
−
−
−
−
−
−
−
SS
)
Max
Î
0.05
0.05
0.05
Î
Î
1.5
Î
3.0
Î
4.0
Î
Î
Î
Î
Î
Î
± 0.1
Î
5.0
Î
—
—
—
10
20
−
−
−
−
−
−
−
−
−
−
−
25C
Min
ÎÎ
−
−
−
ÎÎ
4.95
9.95
ÎÎ
14.95
−
ÎÎ
−
ÎÎ
−
3.5
ÎÎ
7.0
ÎÎ
11
– 2.4
ÎÎ
– 0.51
ÎÎ
– 1.3
– 3.4
ÎÎ
0.51
1.3
ÎÎ
3.4
−
−
ÎÎ
−
−
ÎÎ
−
Typ
(Note 2)
Î
0
0
0
Î
5.0
10
Î
15
2.25
Î
4.50
Î
6.75
2.75
Î
5.50
Î
8.25
– 4.2
Î
– 0.88
Î
– 2.25
– 8.8
Î
0.88
2.25
Î
8.8
±0.00001
5.0
Î
0.005
0.010
Î
0.015
IT = (0.42 A/kHz) f + I
IT = (0.85 A/kHz) f + I
IT = (1.43 A/kHz) f + I
Max
ÎÎ
0.05
0.05
0.05
ÎÎ
−
−
ÎÎ
−
1.5
ÎÎ
3.0
ÎÎ
4.0
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
ÎÎ
−
−
ÎÎ
−
−
ÎÎ
−
± 0.1
7.5
ÎÎ
5.0
10
ÎÎ
20
DD
DD
DD
Min
Î
−
−
−
Î
4.95
9.95
Î
14.95
−
Î
−
Î
−
3.5
Î
7.0
Î
11
– 1.7
Î
– 0.36
Î
– 0.9
– 2.4
Î
0.36
0.9
Î
2.4
−
−
Î
−
−
Î
−
125C
Max
Î
0.05
0.05
0.05
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
± 1.0
Î
Î
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25C.
4. To calculate total supply current at loads other than 50 pF:
) = IT(50 pF) + (CL – 50) Vfk
I
T(CL
where: I
is in A (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
T
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
−
150
300
600
Unit
Î
Vdc
Î
Vdc
Î
Vdc
Î
Î
Vdc
Î
Î
mAdc
Î
Î
Î
mAdc
Î
Adc
pF
Î
Adc
Î
Adc
Î
Î
Î
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