ON Semiconductor MC14015B Technical data

MC14015B

Dual 4−Bit Static Shift Register

The MC14015B dual 4−bit static shift register is constructed with MOS P−Channel and N−Channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4−state serial−input/parallel−output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master−slave flip−flops. Data is shifted from one stage to the next during the positive−going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial−to−parallel conversion where low power dissipation and/or noise immunity is desired.

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PDIP−16

P SUFFIX

CASE 648

16

1

MARKING

DIAGRAMS

MC14015BCP

AWLYYWW

Features

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge−Clocked Flip−Flop Design

• Logic state is retained indefinitely with clock level either high or

low; information is transferred to the output only on the positive going edge of the clock pulse

• Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range

• Pb−Free Packages are Available*

MAXIMUM RATINGS (Voltages Referenced to V

Symbol Parameter Value Unit

V

Vin, V

Iin, I

P

T

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range −0.5 to +18.0 V

DD

Input or Output Voltage Range

out

D

A

stg

L

(DC or Transient)

Input or Output Current

(DC or Transient) per Pin

Power Dissipation, per Package

(Note 1) Ambient Temperature Range −55 to +125 °C Storage Temperature Range −65 to +150 °C Lead Temperature

(8−Second Soldering)

 (Vin or V

SS

or VDD). Unused outputs must be left open.

SS

)  VDD.

out

)

SS

−0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

16

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16 DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX

CASE 966

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

14015B

AWLYWW

1

16

14

015B

ALYW

1

16

MC14015B

AWLYWW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 5

1 Publication Order Number:

MC14015B/D

MC14015B

PIN ASSIGNMENT

Q3

Q2

Q1

Q0

1

C

B

2

B

3

A

4

A

6

R

A

7

D

A

V

8

SS

16

15

14

13

125

11

10

9

C D R Q0 Q

X X 1 0 0

X = Don’t Care Q

= Q0, Q1, Q2, or Q3, as applicable.

n

Q

= Output of prior stage.

n−1

BLOCK DIAGRAM

V

D

R

Q0

Q1

Q2

Q3

C

DD

B

A

7

9

6

15

1

14

TRUTH TABLE

0 0 0 Q 1 0 1 Q X 0 No Change No Change

Q0

D

Q1

Q2

C

Q3

R

Q0

D

Q1

Q2

C

Q3

R

VDD = PIN 16

V

= PIN 8

SS

n

n−1 n−1

5

4

3

10

13

12

11

2

ORDERING INFORMATION

Device Package Shipping

MC14015BCP PDIP−16 500 Units / Rail MC14015BCPG PDIP−16

500 Units / Rail

(Pb−Free) MC14015BD SOIC−16 48 Units / Rail MC14015BDR2 SOIC−16 2500 Units / Tape & Reel MC14015BDR2G SOIC−16

2500 Units / Tape & Reel

(Pb−Free) MC14015BDTR2 TSSOP−16* 2500 Units / Tape & Reel MC14015BFEL SOEIAJ−16 2000 Units / Tape & Reel MC14015BFELG SOEIAJ−16

2000 Units / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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2

MC14015B

Î

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

ОООООООО

Output Voltage “0” Level

V

= VDD or 0

in

ОООООООО

Vin = 0 or V

ОООООООО

DD

“1” Level

Input Voltage “0” Level

= 4.5 or .05 Vdc)

(V

ОООООООО

O

(V

= 9.0 or 1.0 Vdc)

O

ОООООООО

(V

= 13.5 or 1.5 Vdc)

O

(VO = 0.5 or 4.5 Vdc) “1” Level (V

= 1.0 or 9.0 Vdc)

ОООООООО

O

= 1.5 or 13.5 Vdc)

(V

O

Output Drive Current

ОООООООО

(V

= 2.5 Vdc) Source

OH

(V

= 4.6 Vdc)

OH

ОООООООО

(V

OH

(V

OH

= 9.5 Vdc) = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

ОООООООО

(V

= 1.5 Vdc)

OL

Input Current Input Capacitance

ОООООООО

(V

= 0)

in

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current (Notes 3 & 4)

ОООООООО

(Dynamic plus Quiescent, Per Package)

ОООООООО

(C

= 50 pF on all outputs, all

L

ОООООООО

buffers switching)

Symbol

ÎÎ

V

OL

ÎÎ

V

OH

ÎÎ

V

IL

ÎÎ

V

IH

ÎÎ

I

OH

ÎÎ

I

OL

ÎÎ

I

in

C

in

ÎÎ

I

DD

ÎÎ

I

T

ÎÎ

DD

Vdc

Î

5.0 10 15

Î

5.0 10

Î

15

5.0

Î

10

Î

15

5.0 10

Î

15

Î

5.0

Î

10

Î

15

5.0 10

Î

15 15

−

Î

5.0 10

Î

15

5.0

Î

10 15

Î

Min

Î

−

Î

4.95

9.95

Î

14.95

−

Î

−

Î

−

3.5

7.0

Î

11

Î

– 3.0

– 0.64

Î

– 1.6

Î

– 4.2

0.64

1.6

Î

4.2

−

Î

−

Î

−

ООООООООООООООО

SS

− 55C

)

Max

Î

0.05

Î

1.5

Î

3.0

Î

4.0

Î

± 0.1

Î

5.0 10

Î

20

−

25C

Min

ÎÎ

−

ÎÎ

4.95

9.95

ÎÎ

14.95

−

ÎÎ

−

ÎÎ

−

3.5

7.0

ÎÎ

11

ÎÎ

– 2.4

– 0.51

ÎÎ

− 1.3

ÎÎ

− 3.4

0.51

1.3

ÎÎ

3.4

−

ÎÎ

−

ÎÎ

−

Typ

(Note 2)

Î

0 0 0

Î

5.0 10

Î

15

2.25

Î

4.50

Î

6.75

2.75

5.50

Î

8.25

Î

– 4.2

– 0.88

Î

– 2.25

Î

– 8.8

0.88

2.25

Î

8.8

±0.00001

5.0

Î

0.005

0.010

Î

0.015

IT = (1.2 A/kHz)f + I IT = (2.4 A/kHz)f + I IT = (3.6 A/kHz)f + I

Max

ÎÎ

0.05

ÎÎ

−

ÎÎ

−

1.5

ÎÎ

3.0

ÎÎ

4.0

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

± 0.1

7.5

ÎÎ

5.0 10

ÎÎ

20

DD DD DD

Min

Î

−

Î

4.95

9.95

Î

14.95

−

Î

−

Î

−

3.5

7.0

Î

11

Î

– 1.7

− 0.36

Î

– 0.9

Î

− 2.4

0.36

0.9

Î

2.4

−

Î

−

Î

−

125C

Max

Î

0.05

Î

± 1.0

Î

150 300

Î

600

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25C.

4. To calculate total supply current at loads other than 50 pF: ) = IT(50 pF) + (CL − 50) Vfk

I

T(CL

where: I

is in A (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002.

T

−

1.5

3.0

4.0

−

Unit

Î

Vdc

Î

Vdc

Î

Vdc

Î

Vdc

Î

mAdc

Î

mAdc

Î

Adc

pF

Î

Adc

Î

Adc

Î

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3

MC14015B

Î

SWITCHING CHARACTERISTICS (Note 5) (C

= 50 pF, T

L

Characteristic

ООООООООООООО

Output Rise and Fall Time

t

, t

TLH

t

ООООООООООООО

TLH

t

TLH

Propagation Delay Time

ООООООООООООО

Clock, Data to Q

ООООООООООООО

Reset to Q

ООООООООООООО

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

, t

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

t

PLH

= (1.7 ns/pF) CL + 225 ns

PHL

, t

= (0.66 ns/pF) CL + 92 ns

PHL

, t

= (0.5 ns/pF) CL + 65 ns

PHL

, t

= (1.7 ns/pF) CL + 375 ns

PHL

, t

= (0.66 ns/pF) CL + 147 ns

PHL

, t

= (0.5 ns/pF) CL + 95 ns

PHL

Clock Pulse Width

ООООООООООООО

Clock Pulse Frequency

ООООООООООООО

Clock Pulse Rise and Fall Times

ООООООООООООО

Reset Pulse Width

ООООООООООООО

Setup Time

ООООООООООООО

= 25C)

A

Symbol

ÎÎÎ

t

,

TLH

t

THL

ÎÎÎ

t

,

PLH

ÎÎÎ

t

PHL

ÎÎÎ

t

WH

ÎÎÎ

f

cl

ÎÎÎ

t

, t

TLH

THL

ÎÎÎ

t

WH

ÎÎÎ

t

su

ÎÎÎ

V

DD

ÎÎ

5.0 10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10

ÎÎ

15

ÎÎ

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

5.0

ÎÎ

10 15

ÎÎ

5.0 10

ÎÎ

15

5.0 10

ÎÎ

15

Min

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

−

ÎÎ

400 175

ÎÎ

135

−

ÎÎ

−

ÎÎ

−

ÎÎ

400 160

ÎÎ

120 350

100

ÎÎ

75

Typ

(Note 6)

ÎÎ

100

50

ÎÎ

40

ÎÎ

310

ÎÎ

125

ÎÎ

90

ÎÎ

460

ÎÎ

180 120

ÎÎ

185

85

ÎÎ

55

2.0

6.0

ÎÎ

7.5

−

ÎÎ

−

ÎÎ

200

80

ÎÎ

60

100

50

ÎÎ

40

Max

ÎÎ

200 100

ÎÎ

80

ÎÎ

750

ÎÎ

250

ÎÎ

170

ÎÎ

750

ÎÎ

250 170

ÎÎ

−

ÎÎ

−

1.5

3.0

ÎÎ

3.75 15

ÎÎ

5 4

ÎÎ

−

ÎÎ

−

ÎÎ

−

5. The formulas given are for typical characteristics only at 25C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Unit

Î

ns

Î

ns

Î

ns

Î

MHz

Î

s

Î

ns

Î

ns

Î

V

DD

PULSE

GENERATOR

2

PULSE

GENERATOR

1

500 F

I

D

V

Q0

D

Q1 Q2 Q3

C

R

0.01 F CERAMIC

DD

C

L

C

L

V

SS

1 f

CLOCK

50%

DATA

Figure 1. Power Dissipation Test Circuit and Waveform

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4

C

L

C

L

MC14015B

SYNC

PULSE

GENERATOR

2

PULSE

GENERATOR

1

PULSE

GENERATOR

2

PULSE

GENERATOR

1

DATA

INPUT

V

DD

D

Q0

C

Q1

Q2

C

Q3

C

R

V

SS

L

C

L

t

= tWH = 50% Duty Cycle

WL

t

= t

THL

≤ 20 ns

TLH

L

C

L

CLOCK

INPUT

Figure 2. Switching Test Circuit and Waveforms

V

DD

D

Q0

Q1

Q2

C

Q3

C

R

V

SS

L

C

L

C

L

C

L

t

TLH

Q0

CLOCK

INPUT

DATA

INPUT

t

TLH

t

TLH

su

t

WH

t

PLH

50%

t

THL

V

50%

10%

V

DD

0 V

V

DD

0 V

V

0 V

DD

90%

50%

10%

t−

t

THL

90%

50%

10%

t

WL

t

PHL

90%

t

THL

50%

t

su

t

h

0 V

Figure 3. Setup and Hold Time Test Circuit and Waveforms

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5

SINGLE BIT

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6

RESET

CLOCK

DATA

IN

V

DD

V

SS

Q

TO D OF

NEXT BIT

DATA INPUT BUFFER RESET INPUT BUFFER CLOCK INPUT BUFFER

V

DD

V

DD

CIRCUIT SCHEMATICS

MC14015B

DATA

IN

DATA TO

FIRST BIT

V

SS

RESET

IN

V

SS

RESET

TO 4 BITS

CLOCK

IN

V

CLOCK

TO 4 BITS

SS

MC14015B

LOGIC DIAGRAMS

SINGLE BIT

DATA

RESET

DATA INPUT BUFFER

D

7

CLOCK INPUT BUFFER

C

9

R

6

RESET INPUT BUFFER

C

Q

TO D OF NEXT BIT

COMPLETE DEVICE

54 310

Q0 Q1 Q2 Q3

Q

D

Q

C

R

Q0 Q1 Q2 Q3

Q

D

Q

C

R

Q

D

Q

C

R

11 21213

Q

D

Q

C

R

DATA INPUT BUFFER

D

15

CLOCK INPUT BUFFER

C

1

R

14

RESET INPUT BUFFER

Q

D

Q

C

R

Q

D

Q

C

R

Q

D

Q

C

R

D

C

Q

R

VDD = PIN 16

V

= PIN 8

SS

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7

MC14015B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

−A−

916

B

18

F

C

S

SEATING

−T−

PLANE

H

G

D

16 PL

0.25 (0.010) T

K

M

A

L

J

M

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30

L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

M

S

X 45

R



F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7



P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

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8

MC14015B

ÉÉ

PACKAGE DIMENSIONS

TSSOP−16 DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F−01

ISSUE A

0.10 (0.004)

−T−

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

16X REFK

0.10 (0.004) V

M

S

U

T

S

K

K1

16

9

J1

B

−U−

1

8

J

N

A

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

DETAIL E

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

−W−

L 6.40 BSC 0.252 BSC

M 0 8 0 8



INCHESMILLIMETERS

G

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9

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14015B

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE O

L

E

M



L

DETAIL P

VIEW P

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

Q

1

c

2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

INCHES

10



10

0



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MC14015B/D

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ON Semiconductor MC14015B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual