The MC10EL/100EL31 is a D flip-flop with set and reset. The
device is functionally equivalent to the E131 device with higher
performance capabilities. With propagation delays and output
transition times significantly faster than the E131, the EL31 is ideally
suited for those applications which require the ultimate in AC
performance.
Both set and reset inputs are asynchronous, level triggered signals.
Data enters the master portion of the flip-flop when clock is LOW and
is transferred to the slave, and thus the outputs, upon a positive
transition of the clock.
The 100 Series contains temperature compensation.
Features
• 475 ps Propagation Delay
• 2.8 GHz Toggle Frequency
• ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
• PECL Mode Operating Range: V
with VEE = 0 V
• NECL Mode Operating Range: V
with VEE = −4.2 V to −5.7 V
• Internal Input Pulldown Resistors on D, CLK, S, and R
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Metastability 125 ps (see Application Note AN1504)
• Transistor Count = 79 devices
• Pb−Free Packages are Available
= 4.2 V to 5.7 V
CC
= 0 V
CC
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8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
DFN8
MN SUFFIX
CASE 506AA
H = MC10
K = MC100
4T = MC10
2I = MC100
A = Assembly Location
8
1
8
1
MARKING
DIAGRAMS*
8
HEL31
ALYW
G
HL31
ALYWG
G
4T M G
14
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
1Publication Order Number:
MC10EL31/D
MC10EL31, MC100EL31
Table 1. TRUTH TABLE
1
S
8
V
CC
D
S*
R*
CLK
Q
2
D
D
3
45
R
Figure 1. Logic Diagram and Pinout Assignment
Table 3. MAXIMUM RATINGS
S
Q
7
H
X
X
X
L
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
Undef
Z = LOW to HIGH Transition
6
QCLK
R
V
EE
* Pins will default low when left open.
Table 2. PIN DESCRIPTION
PIN
FUNCTION
SECL Set Input
DECL Data Input
RECL Reset Input
CLKECL Clock Input
Q, QECL Data Outputs
V
CC
V
EE
Positive Supply
Negative Supply
EP(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
SymbolParameterCondition 1Condition 2RatingUnit
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
PECL Mode Power SupplyVEE = 0 V8V
NECL Mode Power SupplyVCC = 0 V−8V
PECL Mode Input Voltage
NECL Mode Input Voltage
Output CurrentContinuous
VEE = 0 V
VCC = 0 V
Surge
VI V
VI V
CC
EE
6
−6
50
100
V
V
mA
mA
Operating Temperature Range−40 to +85°C
Storage Temperature Range−65 to +150°C
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
Thermal Resistance (Junction−to−Case)Standard BoardSOIC−841 to 44°C/W
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
Thermal Resistance (Junction−to−Case)Standard BoardTSSOP−841 to 44 ± 5%°C/W
Thermal Resistance (Junction−to−Ambient)0 lfpm
500 lfpm
Wave SolderPb
Pb−Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
DFN8
DFN8
129
84
265
265
°C/W
°C/W
°C
Thermal Resistance (Junction−to−Case)(Note 1)DFN835 to 40°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Output HIGH Voltage (Note 5)392040104110402041054190409041854280mV
Output LOW Voltage (Note 3)305032003350305032103370305032273405mV
Input HIGH Voltage377041103870419039404280mV
Input LOW Voltage305035003050352030503555mV
Input HIGH Current150150150
Input LOW Current0.50.50.3
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.
3. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.
5. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
Output HIGH Voltage (Note 7)391539954120397540454120397540504120mV
Output LOW Voltage (Note 7)317033053445319032953380319032953380mV
Input HIGH Voltage383541203835412038354120mV
Input LOW Voltage319035253190352531903525mV
Input HIGH Current150150150
Input LOW Current0.50.50.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
7. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V.
9. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
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4
MC10EL31, MC100EL31
Table 8. AC CHARACTERISTICS V
= 5.0 V; VEE = 0 V or VCC = 0 V; VEE = −5.0 V (Note 10)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.10 Series: VEE can vary +0.25 V / −0.5 V.
100 Series: VEE can vary +0.8 V / −0.5 V.
Zo = 50 W
Zo = 50 W
Receiver
Device
Driver
Device
QD
QD
50 W50 W
V
VTT = VCC − 3.0 V
TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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5
MC10EL31, MC100EL31
ORDERING INFORMATION
DevicePackageShipping
MC10EL31DSOIC−898 Units / Rail
MC10EL31DGSOIC−8
(Pb−Free)
MC10EL31DR2SOIC−82500 / Tape & Reel
MC10EL31DR2GSOIC−8
(Pb−Free)
MC10EL31DTTSSOP−8100 Units / Rail
MC10EL31DTGTSSOP−8
(Pb−Free)
MC10EL31DTR2TSSOP−82500 / Tape & Reel
MC10EL31DTR2GTSSOP−8
(Pb−Free)
MC10EL31MNR4DFN81000 / Tape & Reel
MC10EL31MNR4GDFN8
(Pb−Free)
MC100EL31DSOIC−898 Units / Rail
MC100EL31DGSOIC−8
(Pb−Free)
MC100EL31DR2SOIC−82500 / Tape & Reel
MC100EL31DR2GSOIC−8
(Pb−Free)
MC100EL31DTTSSOP−8100 Units / Rail
MC100EL31DTGTSSOP−8
(Pb−Free)
MC100EL31DTR2TSSOP−82500 / Tape & Reel
MC100EL31DTR2GTSSOP−8
(Pb−Free)
MC100EL31MNR4DFN81000 / Tape & Reel
MC100EL31MNR4GDFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
†
Resource Reference of Application Notes
AN1405/D− ECL Clock Distribution Techniques
AN1406/D− Designing with PECL (ECL at +5.0 V)
AN1503/D−
AN1504/D− Metastability and the ECLinPS Family
AN1568/D− Interfacing Between LVDS and ECL
AN1672/D− The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
ECLinPSt I/O SPiCE Modeling Kit
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6
−Y−
−Z−
MC10EL31, MC100EL31
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
B
H
A
58
1
4
G
D
0.25 (0.010)Z
M
S
Y
0.25 (0.010)
C
SEATING
PLANE
SXS
M
0.10 (0.004)
M
Y
K
N
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MINMAX
A0.801.00
A10.000.05
A30.20 REF
b0.200.30
D2.00 BSC
D21.101.30
E2.00 BSC
E20.700.90
e0.50 BSC
K0.20−−−
L0.250.35
A
SIDE VIEW
(A3)
C
D2
e/2
1
e
4
L
E2
K
8
5
0.10 C
b8 X
0.05 C
A
BB
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
MC10EL31/D
9
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