ON Semiconductor MC10EL31, MC100EL31 Technical data

MC10EL31, MC100EL31

5 V ECL D Flip‐Flop With Set and Reset

The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131, the EL31 is ideally suited for those applications which require the ultimate in AC performance.

Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

The 100 Series contains temperature compensation.

Features

• 475 ps Propagation Delay

• 2.8 GHz Toggle Frequency

• ESD Protection: > 1 kV Human Body Model,

> 100 V Machine Model

• PECL Mode Operating Range: V

with VEE = 0 V

• NECL Mode Operating Range: V

with VEE = −4.2 V to −5.7 V

• Internal Input Pulldown Resistors on D, CLK, S, and R

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• Metastability 125 ps (see Application Note AN1504)

• Transistor Count = 79 devices

• Pb−Free Packages are Available

= 4.2 V to 5.7 V

= 0 V

http://onsemi.com

SOIC−8 D SUFFIX CASE 751

TSSOP−8

DT SUFFIX CASE 948R

DFN8

MN SUFFIX

CASE 506AA

H = MC10 K = MC100 4T = MC10 2I = MC100 A = Assembly Location

MARKING

DIAGRAMS*

HEL31

ALYW

HL31

ALYWG

4T M G

L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package

KEL31

ALYW

KL31

ALYWG

2I M G

August, 2008 − Rev. 6

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

1 Publication Order Number:

MC10EL31/D

MC10EL31, MC100EL31

Table 1. TRUTH TABLE

CLK

Figure 1. Logic Diagram and Pinout Assignment

Table 3. MAXIMUM RATINGS

H X X X

L L

L L L

Z Z X X X

L H H

Undef

Z = LOW to HIGH Transition

QCLK

* Pins will default low when left open.

Table 2. PIN DESCRIPTION

FUNCTION

S ECL Set Input D ECL Data Input R ECL Reset Input CLK ECL Clock Input Q, Q ECL Data Outputs V

Positive Supply Negative Supply

EP (DFN8 only) Thermal exposed pad

must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.

Symbol Parameter Condition 1 Condition 2 Rating Unit

out

stg

sol

PECL Mode Power Supply VEE = 0 V 8 V

NECL Mode Power Supply VCC = 0 V −8 V

PECL Mode Input Voltage NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V VCC = 0 V

Surge

VI  V VI  V

−6

100

V V

mA mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−8 SOIC−8

190 130

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8 TSSOP−8

185 140

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C <2 to 3 sec @ 260°C

DFN8 DFN8

129

265 265

°C/W °C/W

°C

Thermal Resistance (Junction−to−Case) (Note 1) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

http://onsemi.com

MC10EL31, MC100EL31

Table 4. 10EL SERIES PECL DC CHARACTERISTICS V

= 5.0 V; VEE = 0 V (Note 2)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Ty p Max Unit

Power Supply Current 27 32 27 32 27 32 mA

Output HIGH Voltage (Note 5) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV

Output LOW Voltage (Note 3) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV

Input HIGH Voltage 3770 4110 3870 4190 3940 4280 mV

Input LOW Voltage 3050 3500 3050 3520 3050 3555 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.3

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.

3. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.

Table 5. 10EL SERIES NECL DC CHARACTERISTICS V

= 0 V; VEE = −5.0 V (Note 4)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

Power Supply Current 27 32 27 32 27 32 mA

Output HIGH Voltage (Note 5) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV

Output LOW Voltage (Note 5) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV

Input HIGH Voltage −1230 −890 −1130 −810 −1060 −720 mV

Input LOW Voltage −1950 −1500 −1950 −1480 −1950 −1445 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.3

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / −0.5 V.

5. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.

http://onsemi.com

+ 6 hidden pages