ON Semiconductor MC10EL31, MC100EL31 Technical data

MC10EL31, MC100EL31
5 V ECL D Flip‐Flop With Set and Reset
The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131, the EL31 is ideally suited for those applications which require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.
The 100 Series contains temperature compensation.
Features
475 ps Propagation Delay
2.8 GHz Toggle Frequency
ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
PECL Mode Operating Range: V
with VEE = 0 V
NECL Mode Operating Range: V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors on D, CLK, S, and R
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Metastability 125 ps (see Application Note AN1504)
Transistor Count = 79 devices
PbFree Packages are Available
= 4.2 V to 5.7 V
CC
= 0 V
CC
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8
1
SOIC8 D SUFFIX CASE 751
8
1
TSSOP8
DT SUFFIX CASE 948R
DFN8
MN SUFFIX
CASE 506AA
H = MC10 K = MC100 4T = MC10 2I = MC100 A = Assembly Location
8
1
8
1
MARKING
DIAGRAMS*
8
HEL31
ALYW
G
HL31
ALYWG
G
4T M G
14
L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package
KEL31
ALYW
G
1
8
KL31
ALYWG
G
1
G
2I M G
14
G
© Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 6
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
1 Publication Order Number:
MC10EL31/D
MC10EL31, MC100EL31
Table 1. TRUTH TABLE
1
S
8
V
CC
D
S*
R*
CLK
Q
2
D
D
3
45
R
Figure 1. Logic Diagram and Pinout Assignment
Table 3. MAXIMUM RATINGS
S
Q
7
H X X X
L
L L
H
L
H
L L L
H
H
Z Z X X X
L H H
L
Undef
Z = LOW to HIGH Transition
6
QCLK
R
V
EE
* Pins will default low when left open.
Table 2. PIN DESCRIPTION
PIN
FUNCTION
S ECL Set Input D ECL Data Input R ECL Reset Input CLK ECL Clock Input Q, Q ECL Data Outputs V
CC
V
EE
Positive Supply Negative Supply
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
PECL Mode Power Supply VEE = 0 V 8 V
NECL Mode Power Supply VCC = 0 V −8 V
PECL Mode Input Voltage NECL Mode Input Voltage
Output Current Continuous
VEE = 0 V VCC = 0 V
Surge
VI V VI V
CC
EE
6
6
50
100
V V
mA mA
Operating Temperature Range −40 to +85 °C
Storage Temperature Range −65 to +150 °C
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
SOIC8 SOIC8
190 130
°C/W °C/W
Thermal Resistance (JunctiontoCase) Standard Board SOIC8 41 to 44 °C/W
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
TSSOP8 TSSOP8
185 140
°C/W °C/W
Thermal Resistance (JunctiontoCase) Standard Board TSSOP8 41 to 44 ± 5% °C/W
Thermal Resistance (JunctiontoAmbient) 0 lfpm
500 lfpm
Wave Solder Pb
PbFree
<2 to 3 sec @ 248°C <2 to 3 sec @ 260°C
DFN8 DFN8
129
84
265 265
°C/W °C/W
°C
Thermal Resistance (JunctiontoCase) (Note 1) DFN8 35 to 40 °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
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MC10EL31, MC100EL31
Table 4. 10EL SERIES PECL DC CHARACTERISTICS V
= 5.0 V; VEE = 0 V (Note 2)
CC
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Ty p Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Power Supply Current 27 32 27 32 27 32 mA
Output HIGH Voltage (Note 5) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mV
Output LOW Voltage (Note 3) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mV
Input HIGH Voltage 3770 4110 3870 4190 3940 4280 mV
Input LOW Voltage 3050 3500 3050 3520 3050 3555 mV
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.3
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / 0.5 V.
3. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
Table 5. 10EL SERIES NECL DC CHARACTERISTICS V
= 0 V; VEE = 5.0 V (Note 4)
CC
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Power Supply Current 27 32 27 32 27 32 mA
Output HIGH Voltage (Note 5) 1080 990 −890 980 −895 −810 910 −815 −720 mV
Output LOW Voltage (Note 5) 1950 1800 1650 1950 1790 1630 1950 1773 1595 mV
Input HIGH Voltage −1230 −890 1130 810 1060 720 mV
Input LOW Voltage −1950 1500 1950 −1480 1950 1445 mV
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.3
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.25 V / 0.5 V.
5. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
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MC10EL31, MC100EL31
Table 6. 100EL SERIES PECL DC CHARACTERISTICS V
= 5.0 V; VEE = 0 V (Note 6)
CC
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Power Supply Current 27 32 27 32 31 37 mA
Output HIGH Voltage (Note 7) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV
Output LOW Voltage (Note 7) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV
Input HIGH Voltage 3835 4120 3835 4120 3835 4120 mV
Input LOW Voltage 3190 3525 3190 3525 3190 3525 mV
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / 0.5 V.
7. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
Table 7. 100EL SERIES NECL DC CHARACTERISTICS V
= 0 V; VEE = 5.0 V (Note 8)
CC
40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Power Supply Current 27 32 27 32 31 37 mA
Output HIGH Voltage (Note 9) 1085 1005 880 1025 955 880 1025 −955 880 mV
Output LOW Voltage (Note 9) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mV
Input HIGH Voltage −1165 −880 1165 880 1165 880 mV
Input LOW Voltage −1810 1475 1810 −1475 1810 1475 mV
Input HIGH Current 150 150 150
Input LOW Current 0.5 0.5 0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / 0.5 V.
9. Outputs are terminated through a 50 ohm resistor to VCC−2 volts.
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MC10EL31, MC100EL31
Table 8. AC CHARACTERISTICS V
= 5.0 V; VEE = 0 V or VCC = 0 V; VEE = 5.0 V (Note 10)
CC
40°C 25°C 85°C
Symbol Characteristic Min Ty p Max Min Ty p Max Min Ty p Max Unit
f
max
t
PLH
t
PHL
t
S
t
H
t
RR
t
PW
tJITTER
t
r
t
f
Maximum Toggle Frequency 2.0 2.5 2.2 2.8 2.2 2.8 GHz
Propagation Delay to Output CLK
S, R
Setup Time Hold Time
315
465
295
455
150 2500100
630 630
375
475
355
465
150 2500100
590 590
430 400
530 510
150 2500100
645 645
ps
ps
Set/Reset Recovery 400 200 400 200 400 200 ps
Minimum Pulse Width
400 400 400 ps
CLK, Set, Reset
CycletoCycle Jitter TBD TBD TBD ps
Output Rise/Fall Times Q
100 225 350 100 225 350 100 225 350 ps
(20% 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
10.10 Series: VEE can vary +0.25 V / 0.5 V. 100 Series: VEE can vary +0.8 V / 0.5 V.
Zo = 50 W
Zo = 50 W
Receiver Device
Driver Device
QD
Q D
50 W 50 W
V
VTT = VCC 3.0 V
TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
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MC10EL31, MC100EL31
ORDERING INFORMATION
Device Package Shipping
MC10EL31D SOIC8 98 Units / Rail
MC10EL31DG SOIC8
(PbFree)
MC10EL31DR2 SOIC8 2500 / Tape & Reel
MC10EL31DR2G SOIC8
(PbFree)
MC10EL31DT TSSOP8 100 Units / Rail
MC10EL31DTG TSSOP8
(PbFree)
MC10EL31DTR2 TSSOP8 2500 / Tape & Reel
MC10EL31DTR2G TSSOP8
(PbFree)
MC10EL31MNR4 DFN8 1000 / Tape & Reel
MC10EL31MNR4G DFN8
(PbFree)
MC100EL31D SOIC8 98 Units / Rail
MC100EL31DG SOIC8
(PbFree)
MC100EL31DR2 SOIC8 2500 / Tape & Reel
MC100EL31DR2G SOIC8
(PbFree)
MC100EL31DT TSSOP8 100 Units / Rail
MC100EL31DTG TSSOP8
(PbFree)
MC100EL31DTR2 TSSOP8 2500 / Tape & Reel
MC100EL31DTR2G TSSOP8
(PbFree)
MC100EL31MNR4 DFN8 1000 / Tape & Reel
MC100EL31MNR4G DFN8
(PbFree)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
98 Units / Rail
2500 / Tape & Reel
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
Resource Reference of Application Notes
AN1405/D ECL Clock Distribution Techniques
AN1406/D Designing with PECL (ECL at +5.0 V)
AN1503/D
AN1504/D Metastability and the ECLinPS Family
AN1568/D Interfacing Between LVDS and ECL
AN1672/D The ECL Translator Guide
AND8001/D Odd Number Counters Design
AND8002/D Marking and Date Codes
AND8020/D Termination of ECL Logic Devices
AND8066/D Interfacing with ECLinPS
AND8090/D AC Characteristics of ECL Devices
ECLinPSt I/O SPiCE Modeling Kit
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Y
Z
MC10EL31, MC100EL31
PACKAGE DIMENSIONS
SOIC8 NB
CASE 75107
ISSUE AH
X
B
H
A
58
1
4
G
D
0.25 (0.010) Z
M
S
Y
0.25 (0.010)
C
SEATING PLANE
SXS
M
0.10 (0.004)
M
Y
K
N
X 45
_
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 751−07.
MILLIMETERS
DIMAMIN MAX MIN MAX
4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8
____
N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244
INCHES
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
4.0
0.155
1.270
0.050
SCALE 6:1
ǒ
inches
mm
Ǔ
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MC10EL31, MC100EL31
PACKAGE DIMENSIONS
TSSOP8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R02
ISSUE A
0.10 (0.004)
T
SEATING PLANE
8x REFK
S
U0.15 (0.006) T
2X L/2
85
L
PIN 1 IDENT
S
U0.15 (0.006) T
0.10 (0.004) V
1
4
A
M
B
U
V
S
U
T
S
0.25 (0.010)
M
F
DETAIL E
C
D
G
DETAIL E
W
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.
DIM MIN MAX MIN MAX
A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006
F 0.40 0.70 0.016 0.028 G 0.65 BSC 0.026 BSC K 0.25 0.40 0.010 0.016
L 4.90 BSC 0.193 BSC M 0 6 0 6
____
INCHESMILLIMETERS
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8
MC10EL31, MC100EL31
l
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
8 X
REFERENCE
2 X
SEATING PLANE
PIN ONE
2 X
C0.10
C0.08
C0.10
A1
8 X
D
A
B
E
C0.10
TOP VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF
b 0.20 0.30
D 2.00 BSC D2 1.10 1.30
E 2.00 BSC
E2 0.70 0.90
e 0.50 BSC
K 0.20 −−−
L 0.25 0.35
A
SIDE VIEW
(A3)
C
D2
e/2
1
e
4
L
E2
K
8
5
0.10 C
b8 X
0.05 C
A
BB
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10EL31/D
9
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