ON Semiconductor MC10186 Technical data

MC10186

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Hex D Master-Slave Flip-Flop with Reset

The MC10186 contains six high–speed, master slave type “D” flip–flops. Clocking is common to all six flip–flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive–going Clock transition. Thus, outputs may change only on a positive–going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master–slave construction of this device. A COMMON RESET IS INCLUDED IN THIS CIRCUIT. RESET ONLY FUNCTIONS WHEN CLOCK IS LOW.

• P

= 460 mW typ/pkg (No Load)

D

• f

• t

= 150 MHz (typ)

toggle

, tf = 2.0 ns typ (20%–80%)

r

LOGIC DIAGRAM

D0

2 5

Q0

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16

CDIP–16

L SUFFIX

CASE 620

1

16

PDIP–16

P SUFFIX

CASE 648

1

MARKING

DIAGRAMS

MC10186L

AWLYYWW

MC10186P

AWLYYWW

1

CLOCK

RESET 1

6D1

7D2

10D3

11D4

12

D5

9

CLOCKED TRUTH TABLE

R C D Qn + 1

L L X Q L H* L L L H* H H

H L X L

*A clock H is a clock transition

from a low to a high state.

3 Q1

4 Q2

13 Q3

14 Q4

15 Q5

VCC= PIN 16 V

EE

n

= PIN 8

PLCC–20

FN SUFFIX

CASE 775

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

10186

AWLYYWW

DIP PIN ASSIGNMENT

RESET

Q0

Q1

Q2

D0

D1

D2

V

EE

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion Tables

on page 18 of the ON Semiconductor MECL Data Book

1

2

3

4

5

6

7

8

(DL122/D).

16

15

14

13

12

11

10

V

CC

Q5

Q4

Q3

D5

D4

D3

CLOCK

9

ORDERING INFORMATION

Device Package Shipping

MC10186L CDIP–16 25 Units / Rail MC10186P PDIP–16 25 Units / Rail

MC10186FN PLCC–20 46 Units / Rail

 Semiconductor Components Industries, LLC, 2002

January , 2002 – Rev. 7

1 Publication Order Number:

MC10186/D

MC10186

Und

ELECTRICAL CHARACTERISTICS

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Test Limits

er

Characteristic Symbol

Power Supply Drain Current I Input Current I

E

inH

Test

8 121 88 110 121 mAdc 5

9 1

Output Voltage Logic 1 V

I

inL

OH

5 0.5 0.5 0.3 µAdc

2

15

Output Voltage Logic 0 V

OL

2

15

Threshold Voltage Logic 1 V

OHA

2

15

Threshold Voltage Logic 0 V

OLA

2

15 Switching Times (50Ω Load) ns Propagation Delay t

Rise Time (20 to 80%) t Fall Time (20 to 80%) t

Setup Time t Hold Time t Toggle Frequency (Max) f

1+3–

t

1+4–

t

9+2+

t

9+2–

setup

hold

tog

2+ 2–

 Output level to be measured after clock pulse.

3 4 2 2

2 1.0 4.1 1.1 1.8 4.0 1.1 4.4 2 1.0 4.1 1.1 1.8 4.0 1.1 4.4

2 2.5 2.5 2.5 2.5 ns 2 1.5 1.5 –1.5 1.5 ns 2 125 125 150 125 MHz

V

IL

–30°C +25°C +85°C

Min Max Min Typ Max Min Max

–1.060 –1.060

–1.890 –1.890

–1.080 –1.080

1.6

350 495 920

–0.890 –0.890

–1.675 –1.675

–0.960 –0.960

–1.850 –1.850

–0.980 –0.980

–1.655 –1.655

4.6

V

IH

appears at clock input (Pin 9).

1.6

2.5

3.5

220 310 575

–0.810 –0.810

–1.650 –1.650

–1.630 –1.630

4.5

–0.890 –0.890

–1.825 –1.825

–0.910 –0.910

1.6

–0.700 –0.700

–1.615 –1.615

–1.595 –1.595

220 310 575

5.0

Unit

µAdc

Vdc

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MC10186

ELECTRICAL CHARACTERISTICS (continued)

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TEST VOLTAGE VALUES (Volts)

@ Test Temperature V

IHmax

–30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2

Characteristic Symbol

Power Supply Drain Current I Input Current I

Output Voltage Logic 1 V

Output Voltage Logic 0 V

Threshold Voltage Logic 1 V

Threshold Voltage Logic 0 V

E

inH

I

inL

OH

OL

OHA

OLA

Under

Test

8 8 16 5

9 1

5 5 8 16

2

15

2

15

2

15

2

15

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

V

IHmax

5 9 1

5

12

Switching Times (50Ω Load) +1.11Vdc +0.31V Pulse In Pulse Out –3.2 V +2.0 V Propagation Delay t

Rise Time (20 to 80%) t Fall Time (20 to 80%) t

Setup Time t Hold Time t Toggle Frequency (Max) f

1+3–

t

1+4–

t

9+2+

t

9+2–

setup

hold

tog

2+ 2–

 Output level to be measured after clock pulse.

3 4

6

7 2 2

2 5, 9 2 8 16 2 5, 9 2 8 16

2 5, 9 2 8 16 2 5, 9 2 8 16 2 8 16

V

IH

V

IL

appears at clock input (Pin 9).

V

ILmin

5

12

V

IHAmin

V

IHAmin

12

1, 9 1, 9 5, 9 5, 9

V

ILAmax

V

EE

(VCC)

V

ILAmax

V

EE

Gnd

8 8 8

8 8

5

8 8

5

12

3 4 2 2

8 8

8 8 8 8

16 16 16

16 16

16 16 16 16

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

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