MC10103
Quad 2-Input OR Gate
The MC10103 is a quad 2–input OR gate. The MC10103 provides
one gate with OR/NOR outputs.
• P
= 25 mW typ/gate (No Load)
D
• t
= 2.0 ns typ
pd
• t
, tf = 2.0 ns typ (20%–80%)
r
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LOGIC DIAGRAM
4
5
6
7
12
13
10
11
V
V
PIN ASSIGNMENT
V
CC1
A
OUT
B
OUT
A
IN
A
IN
B
IN
B
IN
V
EE
1
2
3
4
5
6
7
8
CC1
CC2
V
EE
DIP
= PIN 1
= PIN 16
= PIN 8
16
15
14
13
12
11
10
9
MARKING
DIAGRAMS
2
CDIP–16
3
15
9
14
V
CC2
C
OUT
D
OUT
C
IN
C
IN
D
IN
D
IN
C
OUT
MC10103L CDIP–16 25 Units / Rail
MC10103P PDIP–16 25 Units / Rail
MC10103FN PLCC–20 46 Units / Rail
ORDERING INFORMATION
Device Package Shipping
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
16
MC10103L
AWLYYWW
1
16
MC10103P
AWLYYWW
1
1
10103
AWLYYWW
For PLCC pin assignment, see the Pin Conversion Tables on page 18
Pin assignment is for Dual–in–Line Package.
of the ON Semiconductor MECL Data Book (DL122/D).
Semiconductor Components Industries, LLC, 2002
January , 2002 – Rev. 7
1 Publication Order Number:
MC10103/D
MC10103
Und
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
er
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
inH
I
E
inL
OH
Test
8 29 21 26 29 mAdc
4* 390 245 245 µAdc
4* 0.5 0.5 0.3 µAdc
2
9
Output Voltage Logic 0 V
OL
2
9
Threshold Voltage Logic 1 V
OHA
2
9
Threshold Voltage Logic 0 V
OLA
2
9
Switching Times (50Ω Load) ns
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
4+2+
t
12+9–
2+
2–
2
9
2 1.1 3.6 1.1 2.0 3.3 1.1 3.7
2 1.1 3.6 1.1 2.0 3.3 1.1 3.7
* Individually test each input applying VIH or VIL to input under test.
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060
–1.060
–1.890
–1.890
–1.080
–1.080
1.0
1.0
–0.890
–0.890
–1.675
–1.675
–1.655
–1.655
3.1
3.1
–0.960
–0.960
–1.850
–1.850
–0.980
–0.980
1.0
1.0
2.0
2.0
–0.810
–0.810
–1.650
–1.650
–1.630
–1.630
2.9
2.9
–0.890
–0.890
–1.825
–1.825
–0.910
–0.910
1.0
1.0
–0.700
–0.700
–1.615
–1.615
–1.595
–1.595
3.3
3.3
Unit
Vdc
Vdc
Vdc
Vdc
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2
MC10103
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
I
inH
inL
OH
Pin
Under
Test
E
8 8 1, 16
4* 4* 8 1, 16
4* 4* 8 1, 16
2
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
4.5 8
9
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
OL
OHA
2
9
12, 13
2
9
Threshold Voltage Logic 0 V
OLA
2
9
Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
4+2+
t
12+9–
2+
2–
2
9
2 4 2 8 1, 16
2 4 2 8 1, 16
* Individually test each input applying VIH or VIL to input under test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
V
V
ILmin
ILmin
V
IHAmin
V
IHAmin
4, 5
12, 13
12
V
ILAmax
V
EE
(VCC)
V
ILAmax
V
EE
Gnd
1, 16
8
8
8
8
12, 13
8
4, 5 8
8
4
2
9
8
8
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
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3
MC10103
PACKAGE DIMENSIONS
PLCC–20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
–L–
20 1
Z
C
G
G1
0.010 (0.250) N
S
T
–N–
L-M
S
Y BRK
–M–
W
V
A
0.007 (0.180) N
0.007 (0.180) N
R
E
0.004 (0.100)
J
PLANE
SEATING
–T–
VIEW S
S
0.007 (0.180) N
B
0.007 (0.180) N
U
M
S
L-M
T
M
S
S
L-M
T
S
D
Z
D
X
0.010 (0.250) N
G1
S
S
L-M
T
S
VIEW D–D
M
M
S
L-M
T
L-M
T
S
S
S
K1
0.007 (0.180) N
H
M
S
L-M
T
S
K
0.007 (0.180) N
F
M
S
L-M
T
S
VIEW S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
DIM MIN MAX MIN MAX
A 0.385 0.395 9.78 10.03
B 0.385 0.395 9.78 10.03
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC 1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 --- 0.51 ---
K 0.025 --- 0.64 ---
R 0.350 0.356 8.89 9.04
U 0.350 0.356 8.89 9.04
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y --- 0.020 --- 0.50
Z 2 10 2 10
G1 0.310 0.330 7.88 8.38
K1 0.040 --- 1.02 ---
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4
–A–
16 9
–B–
18
–T–
SEATING
PLANE
N
E
F
G
D
16 PL
0.25 (0.010) T
M
A
–A–
916
B
18
F
C
S
–T–
H
G
D
16 PL
0.25 (0.010) T
K
M
MC10103
PACKAGE DIMENSIONS
CDIP–16
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE T
C
K
S
PLASTIC DIP PACKAGE
SEATING
PLANE
M
A
L
M
16 PLJ
0.25 (0.010) T
PDIP–16
P SUFFIX
CASE 648–08
ISSUE R
L
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C --- 0.200 --- 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
M
S
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
M
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
Y14.5M, 1982.
FORMED PARALLEL.
DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
MILLIMETERSINCHES
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5
Notes
MC10103
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6
Notes
MC10103
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7
MC10103
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MC10103/D
8
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