ON Semiconductor MC100LVEP111 Technical data

MC100LVEP111

2.5V / 3.3V 1:10 Differential
ECL/PECL/HSTL Clock Driver

Description

The MC100LVEP111 is a low skew 1-to-10 differential driver,
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
single-ended (if the VBB output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.

The LVEP111 specifically guarantees low output-to-output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.

To ensure tightest skew, both sides of differential outputs identically
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.

The MC100LVEP111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single-ended CLK input operation is limited to a VCC ≥

3.0 V in PECL mode, or VEE v -3.0 V in NECL mode. Designers can
take advantage of the LVEP111's performance to distribute low skew
clocks across the backplane or the board. In a PECL environment, series
or Thevenin line terminations are typically used as they require no
additional power supplies. For more information on using PECL,
designers should refer to Application Note AN1406/D.

Features

•85 ps Typical Device-to-Device Skew

•20 ps Typical Output-to-Output Skew

•Jitter Less than 1 ps RMS

•Maximum Frequency > 3 GHz Typical

•V

Output

BB

•430 ps Typical Propagation Delay

•The 100 Series Contains Temperature Compensation

•PECL and HSTL Mode Operating Range: V

with VEE = 0 V

•NECL Mode Operating Range: V

CC

= 0 V

with VEE = -2.375 V to -3.8 V

•Open Input Default State

•LVDS Input Compatible

•Fully Compatible with MC100EP111

•Pb-Free Packages are Available

= 2.375 V to 3.8 V

CC

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MARKING

DIAGRAM*

MC100

LVEP111

AWLYYWWG

LQFP-32

FA SUFFIX

CASE 873A

32

1

QFN32

MN SUFFIX

CASE 488AM

A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb-Free Package

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

32

1

1

MC100

LVEP111

ALYWG

© Semiconductor Components Industries, LLC, 2007

October, 2007 - Rev. 14

1 Publication Order Number:

MC100LVEP111/D

MC100LVEP111

24 23 22 21 20 19 18 17

V

CC

Q2

Q2

Q1

25

26

27

28

MC100LVEP111

Q1

Q0

Q0

V

CC

29

30

31

32

12345678

CLK0

V

CLK0

BB

CLK1

CLK1

V

CC

CLK_SEL

Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.

Q6Q6Q5Q5Q4Q4Q3 Q3

16

15

14

13

12

11

10

9

Table 1. PIN DESCRIPTION

PIN

CLK0*, CLK0**

V

CLK1*, CLK1**

CC

Q0:9, Q0:9

Q7

CLK_SEL*

Q7

V

CC

V

V

EP

BB

CC

EE

Q8

Q8

Q9

Q9

V

FUNCTION

ECL/PECL/HSTL CLK Input

ECL/PECL/HSTL CLK Input

ECL/PECL Outputs

ECL/PECL Active Clock Select Input

Reference Voltage Output

Positive Supply

Negative Supply

The exposed pad (EP) on the package

bottom must be attached to a heat-sink‐

ing conduit. The exposed pad may only

be electrically connected to VEE.

* Pins will default LOW when left open.
** Pins will default to 2/3VCC when left open.

V

EE

Table 2. FUNCTION TABLE

CLK_SEL

L
H

Active Input

CLK0, CLK0
CLK1, CLK1

Figure 1. LQFP-32 Pinout (Top View)

VCCQ0 Q0 Q1 Q1 Q2 Q2 V

V

1

CC

CLK_SEL

CLK0

CLK0

CLK1

CLK1

2

3

4

5

V

BB

6

7

8

V

EE

V

Q9 Q9 Q8 Q8 Q7 Q7 V

CC

Figure 2. QFN-32 Pinout (Top View)

MC100LVEP111

CC

2526272829303132

24

Q3

23

Q3

22

Q4

21

Q4

20

Q5

19

Q5

18

Q6

17

Q6

1514131211109

16

CC

Exposed Pad (EP)

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2

MC100LVEP111

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection Human Body Model

Machine Model

Charged Device Model

Moisture Sensitivity (Note 1) Pb Pkgs Pb-Free Pkgs

LQFP

QFN

Level 2
Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V-0 @ 0.125 in

Transistor Count 602 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, refer to Application Note AND8003/D.

75 kW

37.5 kW

> 2 kV

> 100 V

> 2 kV

Level 2
Level 1

Q

0

Q

0

CLK0

CLK0

CLK1

CLK1

CLK_SEL

Q

1

Q

1

Q

2

Q

2

Q

3

Q

3

Q

0

1

V

BB

V

EE

V

CC

4

Q

4

Q

5

Q

5

Q

6

Q

6

Q

7

Q

7

Q

8

Q

8

Q

9

Q

9

Figure 3. Logic Diagram

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3

MC100LVEP111

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

EE

V

I

I

out

I

BB

T

A

T

stg

q

JA

q

JC

q

JA

q

JC

T

sol

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

PECL Mode Power Supply VEE = 0 V 6 V

NECL Mode Power Supply VCC = 0 V -6 V

PECL Mode Input Voltage
NECL Mode Input Voltage

Output Current Continuous

VEE = 0 V
VCC = 0 V

Surge

VI ≤ V
VI ≥ V

CC

EE

6

-6

50

100

V
V

mA
mA

VBB Sink/Source ± 0.5 mA

Operating Temperature Range -40 to +85 °C

Storage Temperature Range -65 to +150 °C

Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

LQFP-32
LQFP-32

80
55

°C/W
°C/W

Thermal Resistance (Junction-to-Case) Standard Board LQFP-32 12 to 17 °C/W

Thermal Resistance (Junction-to-Ambient) 0 lfpm

500 lfpm

QFN-32
QFN-32

31
27

°C/W
°C/W

Thermal Resistance (Junction-to-Case) 2S2P QFN-32 12 °C/W

Wave Solder Pb

Pb-Free (QFN-32 Only)

< 3 sec @ 248°C
< 3 sec @ 260°C

265
265

°C

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