ON Semiconductor MC100EPT26 User Manual

MC100EPT26

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

Description

The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board.

The V input mode. In this mode the V

output allows the EPT26 to be used in a Single-Ended

BB

output is tied to the D0 input for a

BB

non-inverting buffer or the D0 input for an inverting buffer. If used, the V

pin should be bypassed to ground with > 0.01ĂmF capacitor.

BB

For a Single-Ended direct connection, use an external voltage reference source such as a resistor divider. Do not use V

BB

for a

Single-Ended direct connection or port to another device.

Features

• 1.4 ns Typical Propagation Delay

• Maximum Frequency = > 275 MHz Typical

• The 100 Series Contains Temperature Compensation

• Operating Range: V

= 3.0 V to 3.6 V with GND = 0 V

CC

• 24 mA TTL outputs

• Q Outputs Will Default LOW with Inputs Open or at V

• V

Output

BB

EE

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

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8

1

SOIC−8 NB

D SUFFIX

CASE 751−07

8

1

TSSOP−8

DT SUFFIX

CASE 948R−02

DFN8

MN SUFFIX

CASE 506AA

MARKING DIAGRAMS*

8

KPT26

ALYW

G

1

SOIC−8 NB TSSOP−8 DFN8

A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D

8

ALYWG

1

KA26

G

1

3W MG

4

.

G

August, 2016 − Rev. 17

ORDERING INFORMATION

Device Package Shipping†

MC100EPT26DG SOIC−8 NB

MC100EPT26DR2G

MC100EPT26DTG 100 Tape & Reel

MC100RPT26DTR2G 2500 Tape & Reel

MC100EPT26MNR4G 1000 Tape & Reel

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D

1 Publication Order Number:

(Pb-Free)

SOIC−8 NB

(Pb-Free)

TSSOP−8

(Pb-Free)

TSSOP−8

(Pb-Free)

DFN8

(Pb-Free)

.

98 Units/Tube

2500 Tape & Reel

MC100EPT26/D

MC100EPT26

1

NC

D

2

LVTTL

3

V

45

BB

LVPECL

(Top View)

Figure 1. 8-Lead Pinout and Logic Diagram

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model Machine Model Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg

SOIC−8 NB TSSOP−8 DFN8

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 117 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

V

78Q0

Q1D

6

GND

CC

Table 1. PIN DESCRIPTION

Pin Function

Q0, Q1 LVTTL Outputs

D0**, D1** Differential LVPECL Inputs Pair

V

CC

V

BB

GND Ground

NC No Connect

EP (DFN8 only) Thermal exposed pad must be con-

** Pins will default to VCC/2 when left open.

Positive Supply

Output Reference Voltage

nected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.

50 kW

> 1.5 kV

> 100 V

> 2 kV

Level 1 Level 3 Level 1

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2

MC100EPT26

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Positive Power Supply GND = 0 V 3.8 V

CC

V

Input Voltage GND = 0 V VI ≤ V

IN

I

VBB Sink/Source ±0.5 mA

BB

T

Operating Temperature Range −40 to +85 °C

A

T

Storage Temperature Range −65 to +150 °C

stg

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W

q

JC

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W

q

JC

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

T

Wave Solder (Pb-Free) 265 °C

sol

Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W

q

JC

500 lfpm

CC

SOIC−8 NB SOIC−8 NB

TSSOP−8 TSSOP−8

DFN8 DFN8

0 to 3.8 V

190 130

185 140

129

84

°C/W

Table 4. PECL INPUT DC CHARACTERISTICS (V

= 3.3 V; GND = 0.0 V (Note 1))

CC

−40°C 25°C 85°C

Symbol

V

IH

V

IL

V

BB

V

IHCMR

I

IH

I

IL

Characteristic

Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV

Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV

Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V

Input HIGH Voltage Common Mode Range (Differential) (Note 2)

Input HIGH Current 150 150 150

Input LOW Current

D D

Min Ty p Max Min Typ Max Min Typ Max

1.2 3.3 1.2 3.3 1.2 3.3 V

−150

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

1. Input parameters vary 1:1 with V

2. V

min varies 1:1 with GND, V

IHCMR

differential input signal.

CC

.

max varies 1:1 with VCC. The V

IHCMR

range is referenced to the most positive side of the

IHCMR

mA

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3

MC100EPT26

Table 5. TTL OUTPUT DC CHARACTERISTICS (V

Symbol

V

OH

V

OL

I

CCH

I

CCL

I

OS

Output HIGH Voltage IOH = −3.0 mA 2.4 V

Output LOW Voltage IOL = 24 mA 0.5 V

Power Supply Current 10 25 35 mA

Power Supply Current 15 34 40 mA

Output Short Circuit Current −50 −150 mA

Characteristic Condition Min Typ Max Unit

= 3.3 V; GND = 0.0 V; T

CC

= −40°C to 85°C)

A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS (V

= 3.0 V to 3.6 V; GND = 0.0 V (Note 1))

CC

−40°C 25°C 85°C

Symbol

f

max

t

,

PLH

t

PHL

t

SK+ +

t

SK− −

t

SKPP

t

JITTER

V

PP

t

r

t

f

Characteristic

Maximum Frequency (Figure 2) 275 350 275 350 275 350 MHz

Propagation Delay to Output Differential (Note 2)

Within Device Skew + + Within Device Skew − − Device-to-Device Skew (Note 3)

Random Clock Jitter (RMS) (Figure 2)

@ ≤ 200 MHz @ > 200 MHz

Input Voltage Swing (Differential Configuration) 150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times (0.8 V−2.0 V) Q, Q

Min Ty p Max Min Typ Max Min Typ Max

1.2

1.5

2.0

1.2

1.5

2.0

1.3

1.7

1.2

1.5

15 20

100

500

6

2030275

1.8

60 85

1.2

1.5

15 20

100

6

4030275

1.8

60 85

500

1.2

100

17030275

1.5

20 30

2.2

1.8

85 85

500

6

330 600 950 330 600 950 330 650 950

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

1. Measured with a 750 mV 50% duty-cycle clock source. R

2. Reference (V

3. Skews are measured between outputs under identical transitions.

= 3.3 V ± 5%; GND = 0 V)

CC

= 500 W to GND and CL = 20 pF to GND. Refer to Figure 3.

L

ns

ps

3.0 VOL  0.5 V

V

OH

2.0

(V)

OH

V

JITTER

1.0

0.0

0 100 200 300

FREQUENCY (MHz)

Figure 2. Typical VOH / Jitter versus Frequency (255C)

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4

12

8

4

RANDOM CLOCK JITTER (ps RMS)

0

MC100EPT26

APPLICATION

TTL RECEIVER

CHARACTERISTIC TEST

*C

includes

L

fixture capacitance

CL*R

GND

L

AC TEST LOAD

Figure 3. TTL Output Loading Used for Device Evaluation

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

ECLinPSt I/O SPiCE Modeling Kit

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

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5

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

1

SCALE 4:1

2X

NOTE 4

PIN ONE

REFERENCE

2X

C0.10

TOP VIEW

DETAIL B

C0.10

C0.08

SIDE VIEW

DETAIL A

1

8

K

e/2

e

BOTTOM VIEW

D

(A3)

D2

A B

E

A

A1

4

SEATING

C

PLANE

8X

L

E2

5

8X

b

0.10 C

0.05 C

DFN8 2x2, 0.5P

CASE 506AA−01

ISSUE E

L1

CONSTRUCTIONS

CONSTRUCTION

A

BB

NOTE 3

L

DETAIL A

OPTIONAL

MOLD CMPDEXPOSED Cu

DETAIL B

OPTIONAL

DATE 22 JAN 2010

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF

b 0.20 0.30

D 2.00 BSC D2 1.10 1.30

E 2.00 BSC E2 0.70 0.90

e 0.50 BSC

0.30 REF

K

L 0.25 0.35 L1 −−− 0.10

GENERIC

MARKING DIAGRAM*

1

XXMG

G

XX = Specific Device Code M = Date Code G = Pb−Free Device

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

RECOMMENDED

SOLDERING FOOTPRINT*

8X

0.50

PACKAGE OUTLINE

1.30

0.90

2.30

1

8X

0.30

DIMENSIONS: MILLIMETERS

0.50 PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98AON18658D

DFN8, 2.0X2.0, 0.5MM PITCH

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

8

1

SCALE 1:1

B

−Y−

−Z−

−X−

A

58

1

4

G

H

D

0.25 (0.010) Z

M

SOLDERING FOOTPRINT*

7.0

0.275

SOIC−8 NB

CASE 751−07

ISSUE AK

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

S

0.25 (0.010)

M

Y

K

Y

C

SXS

SEATING PLANE

0.10 (0.004)

N

X 45

_

M

J

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050

M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

MARKING DIAGRAM*

8

XXXXXX

AYWW

1

Discrete

(Pb−Free)

G

1.52

0.060

4.0

0.155

8

XXXXX ALYWX

1

8

XXXXX ALYWX

G

1

IC

(Pb−Free)

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

8

XXXXXX

AYWW

1

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

0.6

0.024

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

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STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

TSSOP 8

CASE 948R−02

ISSUE A DATE 04/07/2000

0.10 (0.004)

−T−

SEATING PLANE

8x REFK

S

U0.15 (0.006) T

2X L/2

85

L

PIN 1 IDENT

S

U0.15 (0.006) T

0.10 (0.004) V

1

−U−

4

A

M

B

−V−

S

U

T

S

0.25 (0.010)

M

F

DETAIL E

C

D

G

DETAIL E

−W−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006 F 0.40 0.70 0.016 0.028 G 0.65 BSC 0.026 BSC K 0.25 0.40 0.010 0.016 L 4.90 BSC 0.193 BSC M 0 6 0 6

____

INCHESMILLIMETERS

DOCUMENT NUMBER:

DESCRIPTION:

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98AON00236D

TSSOP 8

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ON Semiconductor MC100EPT26 User Manual

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