ON Semiconductor MC100EPT26 User Manual

MC100EPT26

3.3V 1:2 Fanout Differential
LVPECL/LVDS to LVTTL
Translator

Description

The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to
LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are
used only +3.3 V and ground are required. The small outline 8-lead
package and the 1:2 fanout design of the EPT26 makes it ideal for
applications which require the low skew duplication of a signal in a
tightly packed PC board.

The V
input mode. In this mode the V

output allows the EPT26 to be used in a Single-Ended

BB

output is tied to the D0 input for a

BB

non-inverting buffer or the D0 input for an inverting buffer. If used,
the V

pin should be bypassed to ground with > 0.01ĂmF capacitor.

BB

For a Single-Ended direct connection, use an external voltage
reference source such as a resistor divider. Do not use V

BB

for a

Single-Ended direct connection or port to another device.

Features

• 1.4 ns Typical Propagation Delay

• Maximum Frequency = > 275 MHz Typical

• The 100 Series Contains Temperature Compensation

• Operating Range: V

= 3.0 V to 3.6 V with GND = 0 V

CC

• 24 mA TTL outputs

• Q Outputs Will Default LOW with Inputs Open or at V

• V

Output

BB

EE

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

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8

1

SOIC−8 NB

D SUFFIX

CASE 751−07

8

1

TSSOP−8

DT SUFFIX

CASE 948R−02

DFN8

MN SUFFIX

CASE 506AA

MARKING DIAGRAMS*

8

KPT26

ALYW

G

1

SOIC−8 NB TSSOP−8 DFN8

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D

8

ALYWG

1

KA26

G

1

3W MG

4

.

G

© Semiconductor Components Industries, LLC, 2016

August, 2016 − Rev. 17

ORDERING INFORMATION

Device Package Shipping†

MC100EPT26DG SOIC−8 NB

MC100EPT26DR2G

MC100EPT26DTG 100 Tape & Reel

MC100RPT26DTR2G 2500 Tape & Reel

MC100EPT26MNR4G 1000 Tape & Reel

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D

1 Publication Order Number:

(Pb-Free)

SOIC−8 NB

(Pb-Free)

TSSOP−8

(Pb-Free)

TSSOP−8

(Pb-Free)

DFN8

(Pb-Free)

.

98 Units/Tube

2500 Tape & Reel

MC100EPT26/D

MC100EPT26

1

NC

D

2

LVTTL

3

V

45

BB

LVPECL

(Top View)

Figure 1. 8-Lead Pinout and Logic Diagram

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor

ESD Protection

Human Body Model
Machine Model
Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg

SOIC−8 NB
TSSOP−8
DFN8

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 117 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

V

78Q0

Q1D

6

GND

CC

Table 1. PIN DESCRIPTION

Pin Function

Q0, Q1 LVTTL Outputs

D0**, D1** Differential LVPECL Inputs Pair

V

CC

V

BB

GND Ground

NC No Connect

EP (DFN8 only) Thermal exposed pad must be con-

** Pins will default to VCC/2 when left open.

Positive Supply

Output Reference Voltage

nected to a sufficient thermal conduit. Electric­ally connect to the most negative supply (GND)
or leave unconnected, floating open.

50 kW

50 kW

> 1.5 kV

> 100 V

> 2 kV

Level 1
Level 3
Level 1

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MC100EPT26

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Positive Power Supply GND = 0 V 3.8 V

CC

V

Input Voltage GND = 0 V VI ≤ V

IN

I

VBB Sink/Source ±0.5 mA

BB

T

Operating Temperature Range −40 to +85 °C

A

T

Storage Temperature Range −65 to +150 °C

stg

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W

q

JC

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W

q

JC

Thermal Resistance (Junction-to-Ambient) 0 lfpm

q

JA

T

Wave Solder (Pb-Free) 265 °C

sol

Thermal Resistance (Junction-to-Case) (Note 1) DFN8 35 to 40 °C/W

q

JC

500 lfpm

500 lfpm

500 lfpm

CC

SOIC−8 NB
SOIC−8 NB

TSSOP−8
TSSOP−8

DFN8
DFN8

0 to 3.8 V

190
130

185
140

129

84

°C/W

°C/W

°C/W

Table 4. PECL INPUT DC CHARACTERISTICS (V

= 3.3 V; GND = 0.0 V (Note 1))

CC

−40°C 25°C 85°C

Symbol

V

IH

V

IL

V

BB

V

IHCMR

I

IH

I

IL

Characteristic

Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV

Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV

Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 V

Input HIGH Voltage Common Mode
Range (Differential) (Note 2)

Input HIGH Current 150 150 150

Input LOW Current

D
D

Min Ty p Max Min Typ Max Min Typ Max

1.2 3.3 1.2 3.3 1.2 3.3 V

−150

−150

−150

−150

−150

−150

Unit

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

1. Input parameters vary 1:1 with V

2. V

min varies 1:1 with GND, V

IHCMR

differential input signal.

CC

.

max varies 1:1 with VCC. The V

IHCMR

range is referenced to the most positive side of the

IHCMR

mA

mA

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