ON Semiconductor MC100EPT21 User Manual

MC100EPT21

3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.

The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device.

Features

•1.4 ns Typical Propagation Delay

•Maximum Frequency > 275 MHz Typical

•LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs

•24 mA TTL outputs

•Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V

•The 100 Series Contains Temperature Compensation

•VBB Output

•These Devices are Pb−Free and are RoHS Compliant

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			MARKING
			DIAGRAMS*
			8
	8	SO−8	KPT21
		D SUFFIX	ALYW
	1	CASE 751	G
			1
			8
	8	TSSOP−8	KA21
		DT SUFFIX
			ALYWG
	1	CASE 948R
			G
			1
		DFN8	1
			3RMG
		MN SUFFIX
			G
		CASE 506AA

A = Assembly Location

L= Wafer Lot

Y= Year

W= Work Week

M= Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

♥ Semiconductor Components Industries, LLC, 2012	1	Publication Order Number:
September, 2012 − Rev. 22		MC100EPT21/D

MC100EPT21

NC	1		8	VCC
D	2	LVTTL	7	Q
D	3	LVPECL	6	NC
VBB	4		5	GND

Figure 1. Logic Diagram and 8−Lead Pinout (Top View)

Table 2. ATTRIBUTES

Table 1. PIN DESCRIPTION

PIN			FUNCTION
Q			LVTTL/LVCMOS Output
D*,			Differential LVPECL/LVDS/CML Input
	D*
VCC			Positive Supply
VBB			Output Reference Voltage
GND			Ground
NC			No Connect
EP			(DFN8 only) Thermal exposed pad must be
			connected to a sufficient thermal conduit. Elec-
			trically connect to the most negative supply
			(GND) or leave unconnected, floating open.

* Pin will default to 1/2 of VCC when left open.

Characteristics						Value
Internal Input Pulldown Resistor			D			50 kW
Internal Input Pulldown Resistor						50 kW
			D
Internal Input Pullup Resistor	D,					50 kW
		D
ESD Protection	Human Body Model					> 1.5 kV
	Machine Model					> 100 V
	Charged Device Model					> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
	SOIC−8					Level 1
	TSSOP−8					Level 3
	DFN8					Level 1
Flammability Rating	Oxygen Index: 28 to 34					UL 94 V−0 @ 0.125 in
Transistor Count						81 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.

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MC100EPT21

Table 3. MAXIMUM RATINGS

Symbol	Parameter		Condition 1	Condition 2	Rating	Unit
VCC	PECL Power Supply		GND = 0 V		3.8	V
VIN	PECL Input Voltage		GND = 0 V	VI VCC	0 to 3.8	V
IBB	VBB Sink/Source				± 0.5	mA
TA	Operating Temperature Range				−40 to +85	°C
Tstg	Storage Temperature Range				−65 to +150	°C
qJA	Thermal Resistance (Junction−to−Ambient)		0 lfpm	SO−8	190	°C/W
			500 lfpm	SO−8	130	°C/W
qJC	Thermal Resistance (Junction−to−Case)		Standard Board	SO−8	41 to 44	°C/W
qJA	Thermal Resistance (Junction−to−Ambient)		0 lfpm	TSSOP−8	185	°C/W
			500 lfpm	TSSOP−8	140	°C/W
qJC	Thermal Resistance (Junction−to−Case)		Standard Board	TSSOP−8	41 to 44	°C/W
qJA	Thermal Resistance (Junction−to−Ambient)		0 lfpm	DFN8	129	°C/W
			500 lfpm	DFN8	84	°C/W
Tsol	Wave Solder	Pb	< 2 to 3 sec @ 248°C		265	°C
	Pb−Free		<2 to 3 sec @ 260°C		265
qJC	Thermal Resistance (Junction−to−Case)		(Note 2)	DFN8	35 to 40	°C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Table 4. PECL INPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V (Note 3)

			−40°C			25°C			85°C
Symbol	Characteristic	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
VIH	Input HIGH Voltage (Single−Ended)	2075		2420	2075		2420	2075		2420	mV
VIL	Input LOW Voltage (Single−Ended)	1355		1675	1355		1675	1355		1675	mV
VBB	Output Voltage Reference	1775	1875	1975	1775	1875	1975	1775	1875	1975	mV
VIHCMR	Input HIGH Voltage Common Mode	1.2		3.3	1.2		3.3	1.2		3.3	V
	Range (Differential Configuration)
	(Note 4)
IIH	Input HIGH Current			150			150			150	mA
IIL	Input LOW Current	−150			−150			−150			mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

3.Input parameters vary 1:1 with VCC.

4.VIHCMR min varies 1:1 with GND, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.

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MC100EPT21

Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS VCC = 3.3 V, GND = 0.0 V, TA = −40°C to 85°C

Symbol	Characteristic	Condition	Min	Typ	Max	Unit
VOH	Output HIGH Voltage	IOH = −3.0 mA	2.4			V
VOL	Output LOW Voltage	IOL = 24 mA			0.5	V
ICCH	Power Supply Current	Outputs set to HIGH	5	17	25	mA
ICCL	Power Supply Current	Outputs set to LOW	8	21	30	mA
IOS	Output Short Circuit Current		−130		−80	mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0.0 V (Note 5)

						−40°C			25°C			85°C
Symbol	Characteristic				Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
fmax	Maximum Frequency													MHz
	(Figure 2)				275	350		275	350		275	350
tPLH,	Propagation Delay to				800	1400	2050	800	1400	2250	900	1600	2950	ps
tPHL	Output Differential				1200	1400	1800	1200	1400	1800	1100	1300	1900
tSKEW	Duty Cycle Skew (Note 6)				45	50	55	45	50	55	45	50	55	%
tSKPP	Part−to−Part Skew (Note 6)						500			500			500	ps
tJITTER	Random Clock Jitter (RMS)					3.5	5		3.5	5		3.5	5	ps
VPP	Input Voltage Swing				150	800	1200	150	800	1200	150	800	1200	mV
	(Differential Configuration)
tr	Output Rise/Fall Times													ps
tf	(0.8V − 2.0V)	Q,	Q		250	600	900	250	600	900	250	600	900

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5.Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to FIgure 3.

6.Skews are measured between outputs under identical transitions. Duty cycle skew is measured between differential outputs using the deviations of the sum Tpw− and Tpw+.

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