ON Semiconductor MC100EPT21 User Manual

MC100EPT21

3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.

The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, V output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device.

BB

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MARKING

DIAGRAMS*

8

1

8

1

SO−8 D SUFFIX CASE 751

TSSOP−8

DT SUFFIX

CASE 948R

KPT21

ALYW

G

1

8

KA21

ALYWG

G

1

Features

• 1.4 ns Typical Propagation Delay

• Maximum Frequency > 275 MHz Typical

• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs

• 24 mA TTL outputs

• Operating Range: V

= 3.0 V to 3.6 V with GND = 0 V

CC

• The 100 Series Contains Temperature Compensation

• V

Output

BB

• These Devices are Pb−Free and are RoHS Compliant

DFN8

MN SUFFIX

CASE 506AA

A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.

1

3RMG

G

September, 2012 − Rev. 22

1 Publication Order Number:

MC100EPT21/D

MC100EPT21

1

NC

2

D

3

LVPECL

45

V

BB

LVTTL

Figure 1. Logic Diagram and 8−Lead Pinout (Top View)

Table 2. ATTRIBUTES

Internal Input Pulldown Resistor D

Internal Input Pullup Resistor D, D

ESD Protection Human Body Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 81 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

V

CC

78Q

6

NCD

GND

Characteristics Value

Charged Device Model

Table 1. PIN DESCRIPTION

Q

D*, D*

V

CC

V

BB

GND Ground

NC No Connect

EP

* Pin will default to 1/2 of VCC when left open.

Machine Model

SOIC−8

TSSOP−8

DFN8

LVTTL/LVCMOS Output

Differential LVPECL/LVDS/CML Input

Positive Supply

Output Reference Voltage

(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.

FUNCTION

50 kW

> 1.5 kV

> 100 V

> 2 kV

Level 1 Level 3 Level 1

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2

MC100EPT21

Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

V

CC

V

IN

I

BB

T

A

T

stg

q

JA

q

JC

q

JA

q

JC

q

JA

T

sol

q

JC

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

PECL Power Supply GND = 0 V 3.8 V

PECL Input Voltage GND = 0 V VI  V

CC

0 to 3.8 V

VBB Sink/Source ± 0.5 mA

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SO−8 SO−8

190 130

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−8 TSSOP−8

185 140

°C/W °C/W

Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W

Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

Wave Solder Pb

Pb−Free

< 2 to 3 sec @ 248°C <2 to 3 sec @ 260°C

DFN8 DFN8

129

84

265 265

°C/W °C/W

°C

Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Table 4. PECL INPUT DC CHARACTERISTICS V

= 3.3 V, GND = 0.0 V (Note 3)

CC

−40°C 25°C 85°C

Symbol Characteristic

V

IH

V

IL

V

BB

V

IHCMR

Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

Input HIGH Voltage Common Mode Range (Differential Configuration)

Min Typ Max Min Typ Max Min Typ Max

1.2 3.3 1.2 3.3 1.2 3.3 V

Unit

(Note 4)

I

IH

I

IL

Input HIGH Current 150 150 150

Input LOW Current −150 −150 −150

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

3. Input parameters vary 1:1 with VCC.

4. V

min varies 1:1 with GND, V

IHCMR

differential input signal.

max varies 1:1 with VCC. The V

IHCMR

range is referenced to the most positive side of the

IHCMR

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3

MC100EPT21

Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS V

= 3.3 V, GND = 0.0 V, T

CC

= −40°C to 85°C

A

Symbol Characteristic Condition Min Ty p Max Unit

V

I

CCH

I

CCL

I

OS

OH

OL

Output HIGH Voltage IOH = −3.0 mA 2.4 V

Output LOW Voltage IOL = 24 mA 0.5 V

Power Supply Current Outputs set to HIGH 5 17 25 mA

Power Supply Current Outputs set to LOW 8 21 30 mA

Output Short Circuit Current −130 −80 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS V

= 3.0 V to 3.6 V, GND = 0.0 V (Note 5)

CC

−40°C 25°C 85°C

Symbol Characteristic

f

max

t

PLH

t

PHL

t

SKEW

t

SKPP

t

JITTER

V

PP

t

r

t

f

Maximum Frequency (Figure 2) 275 350 275 350 275 350

,

Propagation Delay to Output Differential

Duty Cycle Skew (Note 6) 45 50 55 45 50 55 45 50 55 %

Part−to−Part Skew (Note 6) 500 500 500 ps

Random Clock Jitter (RMS) 3.5 5 3.5 5 3.5 5 ps

Input Voltage Swing (Differential Configuration)

Output Rise/Fall Times

(0.8V − 2.0V) Q, Q 250 600 900 250 600 900 250 600 900

Min Typ Max Min Typ Max Min Typ Max

Unit

MHz

800

1200

1400 1400

2050 1800

800

1200

1400 1400

2250 1800

900

1100

1600 1300

2950 1900

150 800 1200 150 800 1200 150 800 1200 mV

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.

5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to FIgure 3.

6. Skews are measured between outputs under identical transitions. Duty cycle skew is measured between differential outputs using the deviations of the sum Tpw− and Tpw+.

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4

3000

2500

MC100EPT21

V

OH

(mV)

OUTpp

V

2000

VOL  0.5 V

1500

1000

500

0

0 50 100 150 200 250 300 350 400 450 500 550 600

FREQUENCY (MHz)

Figure 2. F

max

APPLICATION

TTL RECEIVER

CHARACTERISTIC TEST

*CL includes

fixture capacitance

CL*R

GND

L

AC TEST LOAD

Figure 3. TTL Output Loading Used For Device Evaluation

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5

MC100EPT21

ORDERING INFORMATION

Device Package Shipping

MC100EPT21DG SOIC−8

(Pb−Free)

MC100EPT21DR2G SOIC−8

(Pb−Free)

MC100EPT21DTG TSSOP−8

(Pb−Free)

MC100EPT21DTR2G TSSOP−8

(Pb−Free)

MC100EPT21MNR4G DFN8

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

98 Units / Rail

2500 / Tape & Reel

100 Units / Rail

2500 / Tape & Reel

1000 / Tape & Reel

†

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

ECLinPSt I/O SPiCE Modeling Kit

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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6

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

1

SCALE 4:1

2X

NOTE 4

PIN ONE

REFERENCE

2X

C0.10

DETAIL B

C0.10

C0.08

SIDE VIEW

DETAIL A

1

8

K

e/2

e

BOTTOM VIEW

D

TOP VIEW

(A3)

D2

A B

E

A

A1

4

SEATING

C

PLANE

8X

L

E2

5

8X

b

0.10 C

0.05 C

DFN8 2x2, 0.5P

CASE 506AA−01

ISSUE E

L1

CONSTRUCTIONS

CONSTRUCTION

A

BB

NOTE 3

L

DETAIL A

OPTIONAL

MOLD CMPDEXPOSED Cu

DETAIL B

OPTIONAL

DATE 22 JAN 2010

NOTES:

L

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.20 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN MAX

A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF

b 0.20 0.30

D 2.00 BSC D2 1.10 1.30

E 2.00 BSC E2 0.70 0.90

e 0.50 BSC

0.30 REF

K

L 0.25 0.35 L1 −−− 0.10

GENERIC

MARKING DIAGRAM*

1

XXMG

G

XX = Specific Device Code M = Date Code G = Pb−Free Device

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

RECOMMENDED

SOLDERING FOOTPRINT*

8X

0.50

PACKAGE OUTLINE

1.30

0.90

2.30

1

8X

0.30

DIMENSIONS: MILLIMETERS

0.50 PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98AON18658D

DFN8, 2.0X2.0, 0.5MM PITCH

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

8

1

SCALE 1:1

B

−Y−

−Z−

−X−

A

58

1

4

G

H

D

0.25 (0.010) Z

M

SOLDERING FOOTPRINT*

7.0

0.275

S

Y

SXS

0.25 (0.010)

C

SEATING PLANE

0.060

0.155

0.10 (0.004)

1.52

4.0

M

Y

N

SOIC−8 NB

CASE 751−07

ISSUE AK

K

X 45

_

M

8

XXXXX ALYWX

1

IC

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

8

XXXXX ALYWX

1

(Pb−Free)

J

G

IC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

GENERIC

MARKING DIAGRAM*

8

XXXXXX

AYWW

1

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

DATE 16 FEB 2011

INCHES

8

XXXXXX

AYWW

G

1

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

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STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

STYLE 19:

STYLE 23:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

www.onsemi.com

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

TSSOP 8

CASE 948R−02

ISSUE A DATE 04/07/2000

0.10 (0.004)

−T−

SEATING PLANE

8x REFK

S

U0.15 (0.006) T

2X L/2

85

L

PIN 1 IDENT

S

U0.15 (0.006) T

0.10 (0.004) V

1

4

A

M

B

−U−

−V−

S

U

T

S

0.25 (0.010)

M

F

DETAIL E

C

D

G

DETAIL E

−W−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006 F 0.40 0.70 0.016 0.028 G 0.65 BSC 0.026 BSC K 0.25 0.40 0.010 0.016 L 4.90 BSC 0.193 BSC M 0 6 0 6

____

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98AON00236D

TSSOP 8

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