ON Semiconductor MC100EP31 User Manual

3.3V/5V ECL D Flip‐Flop with Set and Reset

MC100EP31

Description

The MC100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.

The 100 Series contains temperature compensation.

Features

• 340 ps Typical Propagation Delay

• Maximum Frequency = > 3 GHz Typical

• PECL Mode Operating Range:

= 3.0 V to 5.5 V with VEE = 0 V

• NECL Mode Operating Range:

= 0 V with VEE = −3.0 V to −5.5 V

• Open Input Default State

• Q Output Will Default LOW with Inputs Open or at V

• These Devices are Pb-Free, Halogen Free and are RoHS Compliant

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SOIC−8 NB

D SUFFIX

CASE 751−07

MARKING DIAGRAMS*

KEP31

ALYW

SOIC−8 NB TSSOP−8

TSSOP−8

DT SUFFIX

CASE 948R−02

KP31

ALYWG

K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D

ORDERING INFORMATION

Device Package Shipping

MC100EP31DG

MC100EP31DTG

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D

SOIC−8 NB

(Pb-Free)

TSSOP−8

(Pb-Free)

98 Units / Tube

100 Units / Tube

†

April, 2021 − Rev. 12

1 Publication Order Number:

MC100EP31/D

SET

CLK

RESET

Flip Flop

Figure 1. 8-Lead Pinout (Top View) and

Logic Diagram

MC100EP31

78Q

Table 1. PIN DESCRIPTION

Pin Function

CLK* ECL Clock Inputs

Reset* ECL Asynchronous Reset

Set* ECL Asynchronous Set

D* ECL Data Input

Q, Q ECL Data Outputs

*Pins will default LOW when left open.

Positive Supply

Negative Supply

Table 2. TRUTH TABLE

D SET RESET CLK Q

L H X X X

Z = LOW to HIGH Transition

L L

L H H

Z Z X X X

L H H

UNDEF

Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor

Internal Input Pullup Resistor N/A

ESD Protection

Human Body Model Machine Model Charged Device Model

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg

SOIC−8 NB TSSOP−8

Flammability Rating

Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 75 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

75 kW

> 4 kV

> 200 V

> 2 kV

Level 1 Level 3

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MC100EP31

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

PECL Mode Power Supply VEE = 0 V 6 V

NECL Mode Power Supply VCC = 0 V −6 V

PECL Mode Input Voltage

NECL Mode Input Voltage

Output Current Continuous

out

Operating Temperature Range −40 to +85 °C

Storage Temperature Range −65 to +150 °C

stg

Thermal Resistance (Junction-to-Ambient) 0 lfpm

Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W

Thermal Resistance (Junction-to-Ambient) 0 lfpm

Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W

Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C

sol

VEE = 0 V V

= 0 V

Surge

500 lfpm

VI ≤ V

VI ≥ V

SOIC−8 NB SOIC−8 NB

TSSOP−8 TSSOP−8

−6

100

190 130

185 140

°C/W

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MC100EP31

Table 5. 100EP DC CHARACTERISTICS, PECL (V

= 3.3 V, VEE = 0 V (Note 1))

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Typ Max Min Ty p Max Unit

Power Supply Current 26 34 44 26 35 45 28 37 47 mA

Output HIGH Voltage (Note 2) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

Output LOW Voltage (Note 2) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

Input HIGH Voltage (Single-Ended) 2075 2420 2075 2420 2075 2420 mV

Input LOW Voltage (Single-Ended) 1355 1675 1355 1675 1355 1675 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

2. All loading with 50 W to V

Table 6. 100EP DC CHARACTERISTICS, PECL (V

− 2.0 V.

= 5.0 V, VEE = 0 V (Note 1))

−40°C 25°C 85°C

Symbol Characteristic Min Ty p Max Min Typ Max Min Ty p Max Unit

Power Supply Current 26 34 44 26 35 45 28 37 47 mA

Output HIGH Voltage (Note 2) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

Output LOW Voltage (Note 2) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

Input HIGH Voltage (Single-Ended) 3775 4120 3775 4120 3775 4120 mV

Input LOW Voltage (Single-Ended) 3055 3375 3055 3375 3055 3375 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with V

2. All loading with 50 W to V

− 2.0 V.

. VEE can vary +2.0 V to −0.5 V.

Table 7. 100EP DC CHARACTERISTICS, NECL (V

= 0 V; V

= −5.5 V to −3.0 V (Note 1))

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

Power Supply Current 26 34 44 26 35 45 28 37 47 mA

Output HIGH Voltage (Note 2) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

Output LOW Voltage (Note 2) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

Input HIGH Voltage (Single-Ended) −1225 −880 −1225 −880 −1225 −880 mV

Input LOW Voltage (Single-Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

Input HIGH Current 150 150 150

Input LOW Current 0.5 0.5 0.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Input and output parameters vary 1:1 with VCC.

2. All loading with 50 W to V

− 2.0 V.

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MC100EP31

Table 8. AC CHARACTERISTICS (V

= 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; V

= 0 V (Note 1))

−40°C 25°C 85°C

Symbol

max

Characteristic

Maximum Frequency

Min Ty p Max Min Ty p Max Min Ty p Max

> 3 > 3 > 3 GHz

Unit

(Figure 2)

PLH

PHL

t t

JITTER

Propagation Delay to Output Differential

CLK to Q, Q S, R to Q, Q

250 300

330 380

400 450

270 330

340 400

410 470

300 360

370 430

Set/Reset Recovery 225 225 225 ps

S H

Setup Time Hold Time

100 150

Minimum Pulse width

SET, RESET

Cycle-to-Cycle Jitter

550 450 550 450 550 450

0.2 < 1 0.2 < 1 0.2 < 1 ps

440 500

(Figure 2)

Output Rise/Fall Times

(20% − 80%) 50 120 180 60 130 200 70 150 220

Q, Q

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm.

1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V

−2.0 V.

1100

1000

(mV)

OUTpp

900

800

700

600

500

400

300

200

100

(JITTER)

0 1000 2000 3000 4000 5000 6000

FREQUENCY (MHz)

Figure 2. F

max

/Jitter

ps (RMS)

OUT

JITTER

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MC100EP31

Driver Device

Q D

Figure 3. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D

Resource Reference of Application Notes

AN1405/D − ECL Clock Distribution Techniques

AN1406/D − Designing with PECL (ECL at +5.0 V)

AN1503/D −

AN1504/D − Metastability and the ECLinPS Family

AN1568/D − Interfacing Between LVDS and ECL

AN1672/D − The ECL Translator Guide

AND8001/D − Odd Number Counters Design

AND8002/D − Marking and Date Codes

AND8020/D − Termination of ECL Logic Devices

AND8066/D − Interfacing with ECLinPS

AND8090/D − AC Characteristics of ECL Devices

ECLinPSt I/O SPiCE Modeling Kit

Zo = 50 W

Receiver Device

50 W 50 W

VTT = VCC − 2.0 V

− Termination of ECL Logic Devices)

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

−Y−

−Z−

−X−

0.25 (0.010) Z

SOLDERING FOOTPRINT*

7.0

0.275

0.25 (0.010)

SEATING PLANE

SXS

0.060

0.10 (0.004)

1.52

4.0

0.155

CASE 751−07

SOIC−8 NB

ISSUE AK

X 45

MARKING DIAGRAM*

XXXXX

ALYWX

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

XXXXX ALYWX

(Pb−Free)

DATE 16 FEB 2011

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

INCHES

GENERIC

XXXXXX

AYWW

Discrete

XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

XXXXXX

AYWW

Discrete

(Pb−Free)

0.6

0.024

1.270

0.050

SCALE 6:1

inches

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

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98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 21:

PIN 1. CATHODE 1

2. CATHODE 2

3. CATHODE 3

4. CATHODE 4

5. CATHODE 5

6. COMMON ANODE

7. COMMON ANODE

8. CATHODE 6

STYLE 25:

PIN 1. VIN

2. N/C

3. REXT

4. GND

5. IOUT

6. IOUT

7. IOUT

8. IOUT

STYLE 29:

PIN 1. BASE, DIE #1

2. EMITTER, #1

3. BASE, #2

4. EMITTER, #2

5. COLLECTOR, #2

6. COLLECTOR, #2

7. COLLECTOR, #1

8. COLLECTOR, #1

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

STYLE 22:

PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC

3. COMMON CATHODE/VCC

4. I/O LINE 3

5. COMMON ANODE/GND

6. I/O LINE 4

7. I/O LINE 5

8. COMMON ANODE/GND

STYLE 26:

PIN 1. GND

2. dv/dt

3. ENABLE

4. ILIMIT

5. SOURCE

6. SOURCE

7. SOURCE

8. VCC

STYLE 30:

PIN 1. DRAIN 1

2. DRAIN 1

3. GATE 2

4. SOURCE 2

5. SOURCE 1/DRAIN 2

6. SOURCE 1/DRAIN 2

7. SOURCE 1/DRAIN 2

8. GATE 1

SOIC−8 NB

CASE 751−07

ISSUE AK

STYLE 3:

STYLE 7:

STYLE 11:

STYLE 15:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 19:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. MIRROR 2

7. DRAIN 1

8. MIRROR 1

STYLE 23:

PIN 1. LINE 1 IN

2. COMMON ANODE/GND

3. COMMON ANODE/GND

4. LINE 2 IN

5. LINE 2 OUT

6. COMMON ANODE/GND

7. COMMON ANODE/GND

8. LINE 1 OUT

STYLE 27:

PIN 1. ILIMIT

2. OVLO

3. UVLO

4. INPUT+

5. SOURCE

6. SOURCE

7. SOURCE

8. DRAIN

DATE 16 FEB 2011

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 20:

PIN 1. SOURCE (N)

2. GATE (N)

3. SOURCE (P)

4. GATE (P)

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 24:

PIN 1. BASE

2. EMITTER

3. COLLECTOR/ANODE

4. COLLECTOR/ANODE

5. CATHODE

6. CATHODE

7. COLLECTOR/ANODE

8. COLLECTOR/ANODE

STYLE 28:

PIN 1. SW_TO_GND

2. DASIC_OFF

3. DASIC_SW_DET

4. GND

5. V_MON

6. VBULK

7. VBULK

8. VIN

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42564B

SOIC−8 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

TSSOP 8

CASE 948R−02

ISSUE A DATE 04/07/2000

0.10 (0.004)

−T−

SEATING PLANE

8x REFK

U0.15 (0.006) T

2X L/2

PIN 1 IDENT

U0.15 (0.006) T

0.10 (0.004) V

−U−

−V−

0.25 (0.010)

DETAIL E

−W−

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.

DIM MIN MAX MIN MAX

A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006 F 0.40 0.70 0.016 0.028

G 0.65 BSC 0.026 BSC

K 0.25 0.40 0.010 0.016 L 4.90 BSC 0.193 BSC

M 0 6 0 6

____

INCHESMILLIMETERS

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98AON00236D

TSSOP 8

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

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ON Semiconductor MC100EP31 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual