ON Semiconductor MC100EP31 User Manual
3.3V/5V ECL D Flip‐Flop
with Set and Reset
MC100EP31
Description
The MC100EP31 is a D flip-flop with set and reset. The device is
pin and functionally equivalent to the EL31 and LVEL31 devices.
With AC performance much faster than the EL31 and LVEL31
devices, the EP31 is ideal for applications requiring the fastest AC
performance available. Both set and reset inputs are asynchronous,
level triggered signals. Data enters the master portion of the flip-flop
when CLK is low and is transferred to the slave, and thus the outputs,
upon a positive transition of the CLK.
The 100 Series contains temperature compensation.
Features
• 340 ps Typical Propagation Delay
• Maximum Frequency = > 3 GHz Typical
• PECL Mode Operating Range:
= 3.0 V to 5.5 V with VEE = 0 V
V
CC
• NECL Mode Operating Range:
= 0 V with VEE = −3.0 V to −5.5 V
V
CC
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
EE
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8
1
SOIC−8 NB
D SUFFIX
CASE 751−07
MARKING DIAGRAMS*
8
KEP31
ALYW
G
1
SOIC−8 NB TSSOP−8
8
TSSOP−8
DT SUFFIX
CASE 948R−02
8
KP31
ALYWG
G
1
1
K = MC100
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D
ORDERING INFORMATION
Device Package Shipping
MC100EP31DG
MC100EP31DTG
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
SOIC−8 NB
(Pb-Free)
TSSOP−8
(Pb-Free)
.
.
98 Units / Tube
100 Units / Tube
†
© Semiconductor Components Industries, LLC, 2016
April, 2021 − Rev. 12
1 Publication Order Number:
MC100EP31/D
1
SET
S
D
CLK
RESET
2
3
45
D
Flip Flop
R
Figure 1. 8-Lead Pinout (Top View) and
Logic Diagram
MC100EP31
V
CC
78Q
Q
6
V
EE
Table 1. PIN DESCRIPTION
Pin Function
CLK* ECL Clock Inputs
Reset* ECL Asynchronous Reset
Set* ECL Asynchronous Set
D* ECL Data Input
Q, Q ECL Data Outputs
V
CC
V
EE
*Pins will default LOW when left open.
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
D SET RESET CLK Q
L
H
X
X
X
Z = LOW to HIGH Transition
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
UNDEF
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8 NB
TSSOP−8
Flammability Rating
Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 75 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
75 kW
> 4 kV
> 200 V
> 2 kV
Level 1
Level 3
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2
MC100EP31
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
V
I
T
T
q
q
q
q
T
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
PECL Mode Power Supply VEE = 0 V 6 V
CC
NECL Mode Power Supply VCC = 0 V −6 V
EE
V
PECL Mode Input Voltage
I
NECL Mode Input Voltage
Output Current Continuous
out
Operating Temperature Range −40 to +85 °C
A
Storage Temperature Range −65 to +150 °C
stg
Thermal Resistance (Junction-to-Ambient) 0 lfpm
JA
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W
JC
Thermal Resistance (Junction-to-Ambient) 0 lfpm
JA
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
JC
Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
sol
VEE = 0 V
V
= 0 V
CC
Surge
500 lfpm
500 lfpm
VI ≤ V
CC
VI ≥ V
EE
SOIC−8 NB
SOIC−8 NB
TSSOP−8
TSSOP−8
6
−6
50
100
190
130
185
140
V
mA
°C/W
°C/W
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