ON Semiconductor MC100EP016A Technical data
MC100EP016A
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3.3 V ECL 8-Bit
Synchronous Binary
Up Counter
Description
The MC100EP016A is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the ECLinPS™ family MC100E016 with higher operating
speed.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
Features
•550 ps Typical Propagation Delay
•Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016
•PECL Mode Operating Range: V
with VEE = 0 V
•NECL Mode Operating Range: V
with VEE = -3.0 V to -3.6 V
= 3.0 V to 3.6 V
CC
= 0 V
CC
•Open Input Default State
•Safety Clamp on Clock Inputs
•Internal TC Feedback (Gated)
•Addition of COUT and COUT
•8-Bit
•Differential Clock Input
•V
Output
BB
•Fully Synchronous Counting and TC Generation
•Asynchronous Master Reset
•Pb-Free Packages are Available
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MARKING
DIAGRAMS*
MC100
LQFP-32
FA SUFFIX
CASE 873A
32
1
QFN32
MN SUFFIX
CASE 488AM
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
EP016A
AWLYYWWG
1
MC100
EP016A
AWLYYWWG
G
© Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 9
1 Publication Order Number:
MC100EP016A/D
MC100EP016A
K
K
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V
CC
Q3
Q4
Q5
Q6
Q7
TCLD
V
CC
VCCQ2 Q1 Q0 VEEMR CE PE
1
2
3
4
MC100EP016A
5
6
7
8
1514131211109
V
COUT COUT TC VCCP7 P6 P5
EE
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 32-Lead LQFP Pinout (Top View)
Exposed Pad
(EP)
VCCQ2 Q1 Q0 VEEMR CE PE
2526272829303132
24
23
22
21
20
19
18
17
V
BB
CLK
CLK
P0
P1
P2
P3
P4
V
CC
Q3
Q4
Q5
Q6
Q7
TCLD
V
CC
1
2
3
4
MC100EP016A
5
6
7
8
16
V
COUT COUT TC VCCP7 P6 P5
EE
2526272829303132
24
V
BB
23
CL
22
CL
21
P0
20
P1
19
P2
18
P3
17
P4
1514131211109
16
Figure 2. 32-Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Function
P0-P7 ECL Parallel Data (Preset) Inputs
Q0-Q7 ECL Data Outputs
CE* ECL Count Enable Control Input
PE* ECL Parallel Load Enable Control Input
MR* ECL Master Reset
CLK*, CLK* ECL Differential Clock
TC ECL Terminal Count Output
TCLD* ECL TC-Load Control Input
COUT, COUT ECL Differential Output
V
CC
V
EE
V
BB
EP The exposed pad (EP) on the QFN-32 package bottom is thermally connected to the die for improved
*Pins will default LOW when left open.
Positive Supply
Negative Supply
Reference Voltage Output
heat-sinking conduit. The pad is electrically connected to VEE.
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MC100EP016A
Table 2. FUNCTION TABLE
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CE PE TCLD MR CLK FUNCTION
X
L
L
H
X
X
ZZ = Clock Pulse (High-to-Low)
Z = Clock Pulse (Low-to-High)
Table 3. FUNCTION TABLE
Function PE CE MR TCLD CLK P7-P4 P3 P2 P1 P0 Q7-Q4 Q3 Q2 Q1 Q0 TC COUT COUT
Load Count L
Load Hold L
Load on
Terminal
Count
Reset X X H X X X X X X X L L L L L H H L
L
H
H
H
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
H
X
X
X
X
Z
L
L
L
L
X
X
X
H
H
H
H
H
H
H
Z
X
Z
X
Z
X
Z
X
Z
H
Z
X
Z
X
Z
H
Z
H
Z
H
Z
H
Z
H
Z
H
L
L
L
L
L
H
H
H
X
X
X
X
H
X
X
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
Z
ZZ
X
L
H
X
H
X
H
X
H
X
L
L
H
X
H
X
H
L
H
L
H
L
H
L
H
L
H
L
H
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
H
H
L
L
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
L
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
H
L
L
H
L
H
L
H
L
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
L
H
L
L
L
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MC100EP016A
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PE
TCLD
CE
P
0
MR
CLK
CLK
V
BB
V
EE
BIT 0
Q0M
Q0M
BIT 1
Q
1
BITS 2-6
CE
Q
Q
Q
Q
0
1
Q
2
3
Q
4
5
Q
6
P7
Q
0
SLAVEMASTER
CE
Q
0
P
1
BIT 7
Q
7
TC
5
COUT
COUT
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
Note that this diagram is provided for understanding of logic operation only.
Figure 3. 8‐BIT Binary Counter Logic Diagram
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