Designed primarily for full-wave ac control applications, such as
motor controls, heating controls or dimmers; or wherever full–wave,
silicon gate–controlled devices are needed.
• Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3
• High Commutating di/dt and High Immunity to dv/dt @ 125°C
• Minimizes Snubber Networks for Protection
• Blocking Voltage to 800 Volts
• On-State Current Rating of 12 Amperes RMS at 80°C
• High Surge Current Capability – 100 Amperes
• Industry Standard TO-220AB Package for Ease of Design
• Glass Passivated Junctions for Reliability and Uniformity
• Device Marking: Logo, Device T ype, e.g., MAC12HCD, Date Code
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TRIACS
12 AMPERES RMS
400 thru 800 VOLTS
MT2
MT1
G
MAXIMUM RATINGS (T
RatingSymbolValueUnit
Peak Repetitive Off-State Voltage
(TJ = –40 to 125°C, Sine Wave,
50 to 60 Hz, Gate Open)
On-State RMS Current
(All Conduction Angles; T
Peak Non-Repetitive Surge Current
(One Full Cycle, 60 Hz, T
Circuit Fusing Consideration
(t = 8.33 ms)
Peak Gate Power
(Pulse Width ≤ 1.0 µs, T
Average Gate Power
(t = 8.3 ms, T
Operating Junction Temperature RangeT
Storage Temperature RangeT
(1) V
and V
DRM
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
= 80°C)
C
for all types can be applied on a continuous basis. Blocking
Peak Repetitive Forward Off State Voltage
Peak Forward Blocking Current
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
Maximum On State Voltage
Holding Current
MAC12HCD, MAC12HCM, MAC12HCN
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
on state
at V
I
RRM
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
RRM
Quadrant 3
MainTerminal 2 –
I
H
V
TM
V
I
H
off state
TM
Quadrant 1
MainTerminal 2 +
+ Voltage
I
at V
DRM
DRM
(+) MT2
Quadrant IIQuadrant I
(–) I
GT
GATE
MT1
REF
I
–+ I
GT
(–) MT2
Quadrant IIIQuadrant IV
(–) I
GT
GATE
MT1
REF
(+) I
GATE
(+) I
GATE
(+) MT2
GT
MT1
REF
(–) MT2
GT
MT1
REF
–
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in–phase signals (using standard AC lines) quadrants I and III are used.
GT
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3
MAC12HCD, MAC12HCM, MAC12HCN
100
Q3
Q2
Q1
10
, GATE TRIGGER CURRENT (mA)
GT
I
1
-40-10205080110 125
-255356595
T
, JUNCTION TEMPERATURE (°C)
J
Figure 1. Typical Gate Trigger Current
versus Junction T emperature
100
MT2 NEGATIVE
MT2 POSITIVE
10
1.20
1.10
1.00
0.90
0.80
0.70
0.60
, GATE TRIGGER VOLTAGE (VOLT)
GT
0.50
V
0.40
Q3
Q1
Q2
-40-10205080110 125-255356595
T
, JUNCTION TEMPERATURE (°C)
J
Figure 2. Typical Gate Trigger Voltage
versus Junction T emperature
100
Q2
Q3
Q1
10
HOLDING CURRENT (mA)
1
-40-10205080110 125-255356595-40-10205080110 125-255356595
T
, JUNCTION TEMPERATURE (°C)
J
Figure 3. Typical Holding Current
versus Junction T emperature
125
110
95
, CASE TEMPERATURE ( C)°
80
C
T
65
I
, RMS ONSTATE CURRENT (AMP)
T(RMS)
120°, 90°, 60°, 30°
180°
DC
121086420
Figure 5. Typical RMS Current Derating
LATCHING CURRENT (mA)
, AVERAGE POWER DISSIPATION (WATTS)
(AV)
P
1
T
, JUNCTION TEMPERATURE (°C)
J
Figure 4. Typical Latching Current
versus Junction T emperature
20
18
16
14
12
10
8
6
4
2
0
I
, AVERAGE ONSTATE CURRENT (AMP)
T(AV)
Figure 6. On-State Power Dissipation
DC
180°
120°
90°
60°
30°
121086420
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4
MAC12HCD, MAC12HCM, MAC12HCN
100
10
1
, INSTANTANEOUS ONSTATE CURRENT (AMP)
T
I
0.1
TYPICAL @
T
= 25°C
J
MAXIMUM @ T
0
0.511.522.533.55
VT, INSTANTANEOUS ONSTATE VOLTAGE (VOLTS)
MAXIMUM @ T
= 25°C
J
J
44.5
Figure 7. Typical On-State Characteristics
= 125°C
1
0.1
(NORMALIZED)
r(t), TRANSIENT THERMAL RESISTANCE
0.01
1000010001001010.1
t, TIME (ms)
Figure 8. T ypical Thermal Response
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5
MAC12HCD, MAC12HCM, MAC12HCN
PACKAGE DIMENSIONS
TO–220
CASE 221A–09
ISSUE AA
SEATING
–T–
PLANE
B
4
Q
123
F
T
A
U
C
S
H
K
Z
L
V
R
J
G
D
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM MINMAXMINMAX
A0.570 0.620 14.48 15.75
B 0.380 0.4059.66 10.28
C 0.160 0.1904.074.82
D 0.025 0.0350.640.88
F 0.142 0.1473.613.73
G 0.095 0.1052.422.66
H 0.110 0.1552.803.93
J 0.018 0.0250.460.64
K 0.500 0.562 12.70 14.27
L 0.045 0.0601.151.52
N 0.190 0.2104.835.33
Q 0.100 0.1202.543.04
R 0.080 0.1102.042.79
S 0.045 0.0551.151.39
T 0.235 0.2555.976.47
U 0.000 0.0500.001.27
V 0.045---1.15---
Z--- 0.080---2.04
STYLE 4:
PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 2
3. GATE
4. MAIN TERMINAL 2
MILLIMETERSINCHES
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6
Notes
MAC12HCD, MAC12HCM, MAC12HCN
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7
MAC12HCD, MAC12HCM, MAC12HCN
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MAC12HC/D
8
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