ON Semiconductor LV8344C User Manual

24 V Single-Phase BLDC Motor Driver

LV8344C

INTRODUCTION

Overview

The LV8344C is the driver for 24 V single phase BLDC motor. Its target output duty-cycle can be set by input PWM duty cycle. The output duty-cycle curve setting can be stored to the internal nonvolatile memory (NVM). In addition, lead-angle can also be adjusted by the configuration saved in the internal NVM. Thus, it can drive various kinds of motors at high efficiency and low noise.

Features

• Selectable Soft Start or Direct Output PWM Duty Control in Start-up

• Single-phase Full Wave Driver with Open-loop Output Duty−Cycle

Control

• Embedded Power FETs, I

omax[peak]

= 1.0 A

• PWM Duty Cycle Input (25 Hz to 80 kHz)

• PWM Soft Switching Phase Transition

• Soft PWM Duty Cycle Transitions

(Changing the Target Output−Duty Gradually)

• Built-in Current Limit Function and Over Current Protection

Function

• Built-in Thermal Protection Function

• Built-in Locked Rotor Protection and Automatic Recovery Function

• FG or RD or RDA Signal Output Selectable

• Dynamic Lead Angle Adjustment with Respect to Rotation Speed

• Parameter Setting by Serial Communication

• Embedded EEPROM as NVM

• Parameter Setting to the NVM

• The Device is Pb-Free and Halogen Free

Typical Applications

• Fan Motor in Factory Automation

www.onsemi.com

TSSOP−14

CASE 948AW

PIN ASSIGNMENT

14 RFOUT1 1

13 (NC)PVCC 2

12 OUT2VCC 3

11 GNDREG 4

10 TSLVDD 5

9 PWMIN1 6

8FGIN2 7

(Top View)

MARKING DIAGRAM

LV83

44C

ALYWG

LV8324C = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package

October, 2020 − Rev. 0

ORDERING INFORMATION

Device Package Shipping

LV8344CGR2G TSSOP−14

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

1 Publication Order Number:

(Pb-Free/

Halogen Free)

Tape & Reel

LV8344C/D

†

2,500 /

Application Diagram

Figure 1 shows the application diagram.

LV8344C

Figure 1. Application Diagram

The power supplies of the IC need to be decoupled properly. This means that at least one external capacitor C1 must be connected in between GND and VCC, and one

External Components

Table 1 shows the external component list. Please refer to

section “Pin Description” (Table 7) as well.

external capacitor C2 between REG, VDD and GND.

Table 1. EXAMPLE OF EXTERNAL COMPONENT VALUE FOR 24 V APPLICATION (Figure 1)

Device

D1 1 Anti−reverse connection diode − −

D2 1 Anti−abnormal boost Zener diode − −

C1 1 VCC bypass capacitor

C2 1 REG bypass capacitor

C3 1 Filter of system noise

R1 1 Current limiter resistor for Hall

R2 1 FG pull−up resistor

R3 1 Sense resistor for CLM/OCP

T1 1 Hall element

Qty Description Value Tol Footprint Manufacture

10 mF 50 V

1 mF 25 V

0.1 mF 50 V

2 kW 1/4 W

10 kW 1/4 W

150 mW 1/8 W

10%

Manufacture Part Number

www.onsemi.com

LV8344C

VCC and GND (VCC, GND)

The power supplies of the IC need to be decoupled properly. The following three capacitors must be connected.

• between VCC (pin 3) and ground as C1 in the

application diagrams

• between REG (VDD) and ground as C2

The Zener diode (D2) in Figure 1 is mandatory to prevent the IC break down in case the supply voltage exceeds the absolute maximum ratings due to the flyback voltage.

Hall−Sensor Input Pins (IN1, IN2)

Differential output signals of the hall sensor are connected at IN1 and IN2. It is recommended that the capacitor (C3) is connected between both pins to filter system noise. The value of C3 should be selected properly depending on the system noise. When a Hall IC is used, the output of the Hall IC must be connected to the IN1 pin and the IN2 pin must be kept in the middle level of the Hall IC power supply voltage which should be corresponded to recommended operating range.

Table 2. TRUTH TABLE

IN1 IN2 *Inner PWM state OUT1 OUT2 FG Operation state

L H

H L

*Inner PWM state means the OUTPUT active period decided by inner control logic. Don’t match with PWM−pin input signal. *Condition: Register “DRVMODE [1:0]” = 01

On L H

Off L L Regeneration mode

On H L

Off L L Regeneration mode

Command Input Pin (PWM)

This pin reads the duty cycle of the PWM pulse which controls rotational speed. The PWM input signal level is supported from 2.8 V to 5.5 V. Linear voltage control is not supported. The minimum pulse width is 100 ns.

Current Limiter Resistor for Hall (R1)

Hall output amplitude can be adjusted by R1.

The amplitude is proportional to Hall bias level VH for particular magnetic flux density. VH is determined by the following equation

VH + VREG

Rh ) R1

Where

VREG: REG pin voltage (5 V)

Rh: Hall resistance

However, it should be considered with Hall sensor specification and Hall bias current. The bias current should be set under 20 mA which is REG pin max current.

Hi−Z

Drive mode

(eq. 1)

www.onsemi.com

LV8344C

SPECIFICATIONS

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions Rating Unit

Maximum Supply Voltage VCC

Maximum Output Voltage V

Maximum Output Current (Note 1) I

REG Pin Maximum Output Current I

IN1/IN2 Pin Maximum Input Voltage V

PWM Pin Maximum Input Voltage V

FG Pin Withstanding Voltage V

FG Pin Maximum Current I

Allowable Power Dissipation (Note 2) Pd

Operating Temperature T

Storage Temperature T

Maximum Junction Temperature T

MAX

OUTMAX

REGMAX

INMAX

PWMMAX

FGMAX

MAX

STG

jmax

Moisture Sensitivity Level (MSL) (Note 3) MSL 1 −

Lead Temperature Soldering Pb-Free Versions (30 s or less) (Note 4)

ESD Human Body Model: HBM (Note 5) ESD

SLD

HBM

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. I

2. Specified circuit board: Toroidal shaped. The actual area is 369 mm

is the peak value of the motor supply current.

OUTMAX

internal power and ground plane and 1/2 oz copper traces on top and bottom of the board.

3. Moisture Sensitivity Level (MSL): IPC/JEDEC standard: J−STD−020A.

4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

5. ESD Human Body Model is based on JEDEC standard: JESD22−A114.

Table 4. THERMAL CHARACTERISTICS

Parameter Symbol Value Unit

Thermal Resistance, Junction-to-Ambient without Exposed Pad (Note 2)

Thermal Resistance, Junction-to-Ambient with Exposed Pad (Note 2)

Thermal Resistance, Junction-to-Case (Top) without Exposed Pad (Note 2)

Thermal Resistance, Junction-to-Case (Top) with Exposed Pad (Note 2)

VCC pin 36 V

OUT1/OUT2 pin 36 V

OUT1/OUT2 pin 1.0 A

REG pin 20 mA

IN1/IN2 pin 5.5 V

PWM pin 5.5 V

FG pin 36 V

FG pin 7.5 mA

with exposed pad 0.93

without exposed pad 0.80

−40 to +105 °C

−55 to +150 °C

150 °C

255 °C

±3000 V

, thickness is 0.8 mm and glass epoxy 2-layer board which has 1 oz

156 °C/W

134 °C/W

13.5 °C/W

5.7 °C/W

Table 5. RECOMMENDED OPERATING RANGES

Parameter Symbol Conditions Rating Unit

VCC Supply Voltage VCC

VCC Operating Supply Voltage Range1 VCC

VCC Operating Supply Voltage Range for NVM Program/ Erase Operation

PWM Input Frequency Range F

PWM Minimum Input Low/High Pulse Width T

IN1 Input Voltage Range V

IN2 Input Voltage Range V

VCC

WPWM

OP1

NVM

PWM

IN1

IN2

Minimum External Resister Value R_RFmin 0.15

VCC pin 24 V

TYP

VCC pin 6.0 to 34 V

VCC pin 14 to 34 V

PWM pin 25 to 80k Hz

PWM pin 100 ns

IN1 pin 0 to VDD V

IN2 pin 0.3 to 0.55 × VDD V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

www.onsemi.com

LV8344C

Table 6. ELECTRICAL CHARACTERISTICS (T

Parameter

Circuit Current I

OUT1/OUT2 High-side On-resistance R

OUT1/OUT2 Low-side On-resistance R

OUT1/OUT2 PWM Output Frequency f

PWM Pin Low Level Input Voltage V

PWM Pin High Level Input Voltage V

PWM Input Resolution

PWM Input Bias Current

Symbol Conditions Min Ty p Max Unit

OH-ON

OL-ON

PWMO

PWML

PWMH

PWM

Ipwmin 25 50 75

= 25°C, VCCOP = 24 V unless otherwise noted)

− 8.5 12 mA

IO = 0.3 A − 0.5 0.8

− 48 − kHz

0 − 0.7 V

2.8 − VDD V

− 8 − Bit

(VDD = 5.5 V, PWM = 0 V)

FG Pin On-resistance V

FG Pin Leak Current I

REG Pin Output Voltage V

REG Pin Output Voltage Load

Regulation

Lock-detection Time1 (Note 6) T

Lock-detection Time2 (Note 7) T

Lock-Stop Release Time1

from 1st to 4th Off Time (Note 7)

Lock-Restart On Time (Note 7) T

Lock-Restart Time Ratio1 R

Lock-Stop Release Time2 as from

5th Off Time (Note 8)

Lock-Restart Time Ratio2 as from

Off Time (Note 8)

Thermal Shutdown Protection Detection Temperature

Thermal Shutdown Protection

Detection Hysteresis

Over Current Detection Voltage I

Current Limiter I

Hall Input Bias Current I

Hall Input Sensitivity

FGL

FGLK

REG

REGLD

LD1

LD2

LRoff1

LRon

LR1

LRoff2

LR2

TSD

OVC

hin

DVhin

IFG = 5 mA 60

VCC = 34 V, VFG = 34 V − − 1

4.7 5.0 5.3 V

= −10 mA − − 50 mV

REG

Under rotation − 0.3 − S

Start-up/Restart, LOCK_DET = 3 − 0.95 − S

RESTART_INT = 3 − 9.0 − S

LOCK_DET = 3 − 0.95 − S

LRoff1/TLRon,

RESTART_INT = 3

LOCK_DET = 3,

− 9 − −

− 14 − S

LRoff2/TLRon

, LOCK_DET = 3 − 15 − −

(Guaranteed by design) 150 180 − °C

(Guaranteed by design) − 40 − °C

− 150 − mV

90 100 110 mV

IN1, IN2 = 0 V − − 1

40 − − mV

UVLO Detection Voltage Vuvdet − 5.2 − V

UVLO Release Voltage Vuvrls − 5.6 − V

UVLO Hysteresis Voltage

DVuv

− 0.4 − V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

6. When a motor rotates with below 50 rpm (phase change period over 0.3 s), lock protection will works. See Figure 17 for the detail.

7. When a motor can’t rotate for the time which is set by the register named LOCK_DET after start-up, lock protection will work. See Figure 18 for the detail.

8. When the locked rotor state continues for long time, lock stop period changes as from 5

off time. See Figure 18 for the detail.

www.onsemi.com

BLOCK DIAGRAM

Figure 2 shows the functional block diagram of LV8344C.

LV8344C

OUT1

PVCC

VCC

REG

VDD

IN1

Boot strap

regulator

UVLO

TSD

Pre−driver

Drive control logic

NVM

Current

limitter

Duty Cycle

Counter

SWI

OUT2

SGND

TSL

PWM

IN2

Hall

comparator

OSC

Figure 2. Block Diagram

www.onsemi.com

LV8344C

PIN DESCRIPTION

Table 7 shows the pin list and their functions.

Table 7. PIN LIST AND FUNCTION

Pin No. Pin Name Description

1 OUT1 Motor drive output pin. This pin is connected to the built−in power MOSFET.

2 PVCC Power supply pin for built−in power MOSFET.

3 VCC Power supply for internal circuit, ex. pre−driver, charge−pump.

4 REG

5 VDD Power supply pin for both digital and analog circuits. This pin must be connected to REG pin

6 IN1

7 IN2

8 FG The FG (frequency generator) output controls the motor electrical rotational speed (FG output synchronizes

9 PWM Rotational control signal input pin. The rotational speed is controlled by duty−cycle of the pulse and is propor-

10 TSL Communication input selection and internal test mode pin.

11 SGND Internal circuit ground pin

12 OUT2 Motor drive output pin. This pin is connected to the built−in power MOSFET.

13 NC No connection

14 RF Sense resistor voltage input for current limit / over current protection

5.0 V regulator output. This voltage acts as a power source for oscillator, protection circuits, and so on. The maximum load current of REG is 20 mA. Be sure not to exceed this maximum current

Hall sensor input pin. The differential outputs of the hall sensor need to be connected to IN1 and IN2 each.

with the Hall sensor signal). This pin can function as RD (rotation detection) and RDA (Rotation Decline Alarm ) by bit setting of Reg. 0x010C “TACHSEL”. The FG pin is an open drain output. Recommended pull up resistor is 1 kW to 100 kW. Leave the pin open when not in use. Parameter setting through the communication is performed by the pin use

tional to the duty−cycle ratio. Parameter setting through the communication is performed by this pin

When short to GND, FG pin is serial in/out. When short to REG, PWM pin is serial in and FG pin is for serial out

SIMPLIFIED EQUIVALENT CIRCUITS

Table 8 shows the pin information. The pull-up/down resistor and diode path are included.

Table 8. PIN EQUIVALENT CIRCUIT

(OUT+4.5 V)

VDD

OUT1, OUT2

PVCC

OUT1

OUT2

SGND

PVCC

VCC

SGND

PVCC, VCC/SGND

www.onsemi.com

Table 8. PIN EQUIVALENT CIRCUIT (continued)

LV8344C

VCC

SGND

VCC

IN 1

SGND

REG

IN1

VDD

REG

SGND

IN2

VDD

IN 2

SGND

VCC

VDD

SGND

VDD

TSL

GND

TSL

VCC

VDD

PWM

SGND

VDD

SGND

Low

PWM

96k

www.onsemi.com

LV8344C

OPERATION DESCRIPTION

The LV8344C has various functions and parameters which are defined by built-in registers. Refer to the Register map and description page for the detail.

Spin-up Sequence

To spin-up a motor, power is applied to VCC pin and the appropriate input PWM signal (see “DUTY_L” and“DUTY_S” setting description in section “Steady Rotation”) is applied to PWM pin. The LV8344C starts driving the motor whose current direction is determined by the Hall sensor signal.

To avoid the unnecessary rush current, the “soft start” mode is provided, which gradually increases output duty-cycle. After the soft start mode, LV8344C goes to steady rotation mode. The detail of the soft start mode and steady rotation mode are described in the sections below.

In addition, soft switch function in start-up mode is available. In case of “SS_SW_SEL = 0”, falling time of duty-cycle is 5 ms and rising time is 2.5 ms. In case of “SS_SW_SEL = 1”, each time is half of the case of “SS_SW_SEL = 0”.

If a motor already rotates at the power on in faster speed than 304 rpm, the soft start mode is skipped and goes to steady rotation mode immediately.

Soft Start

For soft start mode, the duty-cycle ramp up profile is defined by the initial duty-cycle, slope, and exit condition. The initial duty-cycle is fixed and it starts from 4%. The slope is programmable. It is determined by registers “SSTART_SEL” and “INCTIM”. The duty-cycle is increased up to the end duty-cycle “SSTART_SEL” for duration time “INCTIM”. The end duty-cycle is selectable at 0%, 24%, 54% or 80% (see Table 9). The duration time can be selected from 0.0002 sec to 15.2 s (see Table 10). The exit condition means it’s in the state of either the duty-cycle reaches “SSTART_SEL”. Soft start operation requires at least 8 electrical cycles (4 mechanical cycles in case of 4 poles single phase motor) independent on the exit condition.

Table 9. SOFT START END DUTY-CYCLE

SSTART_SEL End Duty-cycle

0 0% output duty-cycle (Disable Soft Start)

1 24% output duty-cycle

2 54% output duty-cycle

3 80% output duty-cycle

Table 10. SOFT START DURATION TIME

INCTIM Duration Time (s)

SSTART_SEL = 1

[2] [1] [0] SSTART_SEL = 0

0 0 0 0 0.0002 0.10 0.15

0 0 1 0 0.48 0.50 0.76

0 1 0 0 0.96 1.00 1.52

0 1 1 0 1.50 1.50 2.28

1 0 0 0 2.00 2.00 3.04

1 0 1 0 3.00 3.00 4.56

1 1 0 0 5.00 5.00 7.60

1 1 1 0 10.0 10.0 15.2

(End Duty-cycle = 24%)

SSTART_SEL = 2

(End Duty-cycle = 54%)

SSTART_SEL = 3

(End Duty-cycle = 80%)

www.onsemi.com

+ 20 hidden pages