ON Semiconductor LC786830 User Manual

LC786830 Demo Board Kit User's Manual
EVBUM2769/D
Overview
This manual provides detailed information about the use and the configuration of the LC786830 Demo Board Kit to help you evaluate the performance and capabilities of LC786830 in developing application software for it.
LC786830 Demo Board Kit comprises Main Board, LCD Board and Downloader Board. The Main Board features miscellaneous components to show the performance of LC786830. The LCD Board has buttons as well as a LCD module for user interface.
Hardware
Main Board
LC786830
Power Supply
Memory
Bluetooth on Board Module
Audio
Interfaces
LCD Board
LCD Module
Key Button (2 x 4)
Downloader Board
Microcontroller
USB TypeB Connector
audio, and handsfree communication.
12 V/4 A DC Jack (2.1 mm center positive)LDO 1.2 V/3.3 V/5.0 V/8.0 V
16 Mbit QSPI Flash32 Mbit QSPI Flash256 kbit EEPROM64 Mbit PSRAM (optional)
ECM with Op AmpExternal DAC (Fs: 192 kHz)Piezo SpeakerRCA Jack3.5 mm Phone Jack
USB TypeA ConnectorSD Card Socket (on the solder side)IR ReceiverDebugJTAG 20Pin Connector (SWD)
Rotary Encoder
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EVAL BOARD USER’S MANUAL
LCD Board Main Board
Downloader Board
Figure 1. LC786830 Demo Board Kit
Semiconductor Components Industries, LLC, 2020
January, 2021 Rev. 1
1 Publication Order Number:
EVBUM2769/D
EVBUM2769/D
LCD Board
Connector
Downloader
Board
Connector
12 V DC Jack
IR Receiver
CD Board Connector
ECM
LC786830
Bluetooth Module
Phone Jack
Figure 2. LC786830 Demo Main Board
Figure 3. Block Diagram of LC786830 Demo Main Board
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2
EVBUM2769/D
Power Supply
The enable pins of three LDOs on the Main Board are connected to pins of LC786830 via jumpers. Thus, place shunt jumpers on pins 2 and 3 of JP1, JP2 and JP3 before powering the Main Board except when each state can be set by GPs. Refer to the following table and figure. After that, connect the plug of a 12 V power supply to the DC jack (CN501, center positive, up to 4 A).
Table 1. JPS OF POWER SOURCE
Jumper Name Function Jumper Pin # State
JP1 Enable 3.3 V
(DVDD2)
JP2 Enable 5 V
(5V)
JP3 Enable 8 V
(CDV)
Figure 4. The Locations of JPs
Programing the Flash on the Board
1 GP00_1
3 ON
1 GP00_2
3 ON
1 GP00_0
3 ON
JP2
JP1
JP3
The Flash Writer Application can program the flash memory on the Main Board from your PC over the Downloader Board. The Flash Write Application is available from the onsemi.com website.
Applications
Bluetooth module NF2210EZ is embedded on the Main Board with printed antenna so that it is easy to establish a Bluetooth connection with a phone or other device. An electret condenser microphone is also embedded on the Board for handsfree communication. It has a gain of 40 dB. If you do not achieve that in your environment, please replace resistors, R662 and R665 to adjust the gain. Although the builtin DAC of the LC786830 supports up to 96 kHz sampling rates, external DACs which can accept 192 kHz sampling rates also are featured on the Board so that 192 kHz sampling rates playback is acceptable. When the output level of GP04_4 is low, builtin DAC outputs are connected with RCA jack. When the output level of GP04_4 is high, external DAC outputs are connected with RCA jack. Refer to the schematic of the Main Board. The 3.5 mm phone jack is connected to a differential input on the LC786830 to accept an analog input. The Main Board also has an EEPROM for backup applications such as storing volume settings. The SD Card socket is embedded on the solder side as well. The Main Board can mount PSRAM but the PSRAM needs to use same ports of LC786830 as the SD Card control. Therefore, when PSRAM is available, the SD Card solution is not available. In addition to that, there are a piezo speaker and an IR receiver on the Main Board for applications. Furthermore, the Main Board can be connected with ON Semiconductor’s CD playback Board so that it is easy to support a CD solution. A dedicated IIC interface is available for MFi, via a CN102A terminal on the Main Board.
For details of each component on the Boards, refer to its datasheet.
Debugging
A Serial Wire Debug interface is available for debugging. CN103 (JTAG 20pin connector) on the Main Board is its adaptor connector.
M0+ Code File
Process Indicator (%)
Figure 5. Flash Writer Application
Figure 6. Connect the Downloader Board to your PC
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Table 2. CN103 PIN ASSIGNMENT
CN103 Pin# Name Function
7 SWDIO SWD data I/O
9 SWCLK SWD clock
1, 2 3.3 V Power
4, 6, 8, 10, 12, 14,
16, 18, 20
Figure 7. Debugger Connected with CN103
GND Ground
Also, TP108 (TX0), TP109 (RX0), are prepared for UART data logger monitor use in debugging.
3
EVBUM2769/D
DSP Port Assignment
The General Ports of LC786830 are assigned according to the table shown below. Refer to the table and schematics, when developing application software.
Table 3. GP ASSIGNMENT TABLE
Name Function I/O Usage
GP00_0 GPIO O Enable 8 V (CDV)
GP00_1 GPIO O Enable 3.3 V (DVDD2)
GP00_2 GPIO O Enable 5 V (5V)
GP00_3 IRQ I Detect KEY0 input
GP00_4 IRQ I CD (mechanicalsw1)
GP00_5 IRQ I CD (mechanicalsw2)
GP00_6 IRQ I DISPLAY (TIRQ)
GP00_7 TIMER I IR Receiver
GP01_0 IIC O EEPROM SCL
GP01_1 IIC I/O EEPROM SDA
GP01_2 GPIO O CD (S/L selector)
GP01_3 TIMER O Piezo Speaker
GP01_4 GPIO O CD (Driver Mute/active low)
GP01_5 GPIO O CD (Loader plus)
GP01_6 GPIO O CD (Loader minus)
GP01_7 GPIO I
GP02_0 GPIO O USB (VBUS Disable/active low)
GP02_1 GPIO I USB (Detect Over Current)
GP02_2 GPIO O DISPLAY (TCE)
GP02_3 SIO O DISPLAY (TDIN)
GP02_4 SIO O DISPLAY (TCLK)
GP02_5 SIO I DISPLAY (TDO)
GP02_6 UART O Debug (M0+ TX)
GP02_7 UART I Debug (M0+ RX)
GP03_0 GPIO O DISPLAY (Enable LCDPower)
GP03_1 GPIO O DISPLAY (LCDCE)
GP03_2 GPIO O DISPLAY (LCDRESET)
GP03_3 GPIO O DISPLAY (LCDD/C)
GP03_4 SIO O DISPLAY (LCDCLK)
GP03_5 SIO I DISPLAY (LCDDO)
GP03_6 SIO O DISPLAY (LCDDIN)
GP04_2 GPIO I RotaryEncoder A
GP04_3 GPIO I RotaryEncoder B
GP04_4 GPIO O Select Builtin/External DACs
GP04_5 GPIO I
GP04_6 GPIO I
GP04_7 GPIO I
GP05_0 A/D I KEY0 input
Table 3. GP ASSIGNMENT TABLE (continued)
Name
GP05_1 A/D I KEY1 input
GP05_2 A/D I KEY2 input
GP05_3 A/D I KEY3 input
GP05_4 GPIO I
GP05_5 GPIO I
GP05_6 GPIO I
GP05_7 GPIO I
Function I/O Usage
LCD Board
Figure 8.
LCD module is mounted on the LCD Board.
Refer to the following table for a description of the signal names. For more information about the components of the LCD module, refer to their respective datasheets.
Table 4. LCD MODULE SIGNALS
Signal Name I/O Description
LED I Enable backlight
CS I Module CS, active low
RESET I Module Reset, active low
D/C I High: transmit data
MOSI I SPI Master Out Slave In
MISO O SPI Master In Slave Out
SCK I SPI clock
TIRQ O Touch module,
TCS I Touch module CS, active low
TDIN I Touch module
TDO O Touch module
TCLK I Touch module
Low: transmit command
Touch detector, active low
SPI Master Out Slave In
SPI Master In Slave Out
SPI clock
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4
Downloader Board
EVBUM2769/D
The microcontroller on the Board supports programing of the flash on the Main Board from your PC. Place shunt jumpers on pins 2 and 3 of JP101 and turn all switches of DSW1 off. Reset switch, TSW1 controls the reset status of the Microcontroller. The reset is active low. With the Downloader Board connected to the Main Board, TSW1 must be turned to L (low) when debugging.
Figure 9.
LAYOUT
Figure 10. Layout of the Main Board of LC786830 Demo Board Kit (Top View)
Figure 11. Layout of the Main Board of LC786830 Demo Board Kit (Bottom View)
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EVBUM2769/D
SCHEMATICS AND BILL OF MATERIALS
7
VCC
HLDB
CSB
7
VCC
HLDB
CSB1DO2WPB
DGND
RE−B
GP04−2
GP04−3
4 5 3 2 1
DVDD
6DI5
3
6DI5
3
GP05AD0
KEY0
TEST0
C184 0.1
DGND
20
2
4
6
8
10
12
14
16
18
G
Vsply
Vtref
nTRST
CN103
1
3
OPEN
CLK
WPB
GND
W25Q32JVSSIQ
4
CLK
R194 4.7K
GND
W25Q16JVSSIQ
4
C183 OPEN
OPEN
C182
OPEN
C181 C180 OPEN
1000pF
C179
1000pF
C178
1000pF
C177 C176 1000pF
P104 P103 P102
33K
R109 R107 33K
GP05AD3
GP044
GP05AD1
GP05AD2
KEY1
KEY2
KEY3
DACSEL
GP04−4
GP05AD3
GP05AD2
GP05AD1
GP05AD0
TP117 TP116 TEST0
TEST1
TEST2
TEST3
DGND
G
G
G
G
G
G
G
G
TDI
TMS
TCK
RTCK
TDO
nSRST
RQ
ACK
SWD
5
7
9
11
13
15
17
19
SWCLK
SWDIO
100
100
R168
R167
R166 R165 OPEN
M0SWDIO
M0SWCLK
TP120
TP121
DGND
0.1
C195
C194 0.1
C564
100u/10v
C120 0.1
C119 0.1
C563 100u/10v
0.1
C118
C117
0.1
0.1
C116
C115 0.1
C114 0.1
5V
IC107
SL:Low A
R140 10K R139
10K
R138
10K 10K
R137
GP04−0
M3SWCLK
C143 0.1
15
16
Vcc
OEB
SL
11A21B31Y42A52B62Y7
DGND
GP05AD5
GP05AD6
GP05AD7
GP05AD4
GP05AD7
GP05AD4
GP05AD5
GP05AD6
R142
10K
DVDD
GP04−1
GP07−7
M3SWDIO
TEST3
TEST2
uCTEST2
uCTEST3
uCMDCTL
uCTEST1
uCTEST0
TEST2
TEST3
TP118
TP119
93B103A114Y124B134A14
3Y
GND
74FST3257
8
DGND DGND
R141 10K
DGND
CN102B
WL−8DGND
1234567
8
0
R158
R159 OPEN
CN102A
8
VDD
CEB
IC105
1
CDDI CDDO CDCL CDCE SBCKO PWI SFSYI SBSYI
OPCDM CDLRCK CDBCK CDDATA CDBUSYB CDRESB
P120
CPSCL CPSDA
P122 P123
1234567
R154 10K
R155 R156
7
6
5
SCLK
SIO[3]
SI/SIO[0]
VSS
SO/SIO[1]2SIO[2]
3
4
IC101
LC786830
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
172
173
174
175 176 177 178 179 180 181 182 183 184 185 186 187 188
189
190
191
192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
DGND
SDA
SCL
WL−8
8
2.2K
R157
DGND
C196 0.1
DGND
IPS6404LSQSPN
Not mounted
DGND
0.1
0.1
C131
C132
C566 OPEN(100u/10v)
155
154
156
153
DVSS
DVDD
GP10_0 GP10_1 GP10_2 GP10_3 GP10_4 GP10_5 GP10_6 GP10_7 GP11_0 GP11_1 GP11_2 GP11_3 GP11_4 GP11_5 GP11_6 GP11_7
DVDD12
DVSS
DVDD
GP12_0 GP12_1 GP12_2 GP12_3 GP12_4 GP12_5 GP13_0 GP13_1 GP13_2 GP13_3 GP13_4 GP13_5 GP13_6 GP13_7
DVDD12
DVSS
DVDD
GP14_0 GP14_1 GP14_2
GP14_3 RESB L1IN R1IN L2IN R2IN
L3INP L3INN R3INP R3INN L4INP L4INN R4INP R4INN
MICINP
AVDD12AVSS11AVDD27AVSS2
3
4
10u/50v
10u/50v
C162
C161
MICINP
0.1
OPEN(100u/25v)
C101
C151
C152 47u/50v
DVDD2
2.2K
2.2K
DVDD2
DVDD2
HCIRESB
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
SDDET
SDWP
SDDAT2
SDDAT3
SDCMD
SDCLK
SDDAT0
SDDAT1
0
R118
0
R119
0
R120
0
R121
0
R122 R123
HCI_SCL
BUSYB
CD BUS
C561
C562
0
OUTPUT INPUT
10u/50v
10u/50v
10u/50v
10u/50v
OPEN(10u/50v)
OPEN(10u/50v)
C168
C169
C170
C164
C163
C167
L1IN
R1IN
RESB
L3INP
R3INP
L3INN
R3INN
TP115
TP114
CDSW1 CDSW2 S/L DMUTEB LM+ LM
DGND DGND
2.2K R161
2.2K HCI_SDA
R162
DVDD2
0.1
C133
C134 0.1
30_RTS
30_CTS
30_RX
30_TX
DVDD2
R163
OPEN
R164 OPEN
C135 0.1
C136 0.1
100u/10v
100u/10v
DVDD
AVDD
DVDD1.2V
220pF
OPEN(100u/10v)
C140
C565
P119
151
152
AFILT1
GP09_7
DVDD12
VREF_ADC
MICINN
5
6
VREF_ADC
MICINN
0.1
C102
5V
150
0.1
C103
GP09_6
149
GP09_5
DACOUT1L
8
DACOUT1L
100u/25v
C153
CN101
4700pF
C139
R117 1.5K
1K
R115
147
148
GP09_3
GP09_4
DACOUT1R9DACOUT2L
DACOUT1R
VBUS
1D2D+3
UDP1
TEST3
146
145
144
UDP1
TEST3
GP09_2
DACOUT2R13DACOUT_S16VREF_DAC17AVDD311AVSS310AVDD415AVSS4
12
DACOUT2L
DACOUT2R
0.1
C104
C154 OPEN(100u/25v)
4
UDM1
143ID141
14
GND
0.1
C130
142
UDM1
UVDD1
0.1
C105
USB TYPE A
DGND
5V
C129 0.1
2.2K
R116
140
139
VBUS
UVSS1
18
DACOUTS
VREF_DAC
OPEN(100u/25v)
47u/50v
0.1
C155
C156
C106
5V
220u/25v
C173
4
6
5
FLG
OUT
ILIM
IN
GND2EN
IC106
NCV380H(UDFN6)
1
3
0.1
DGND
C171
C172 100u/25v
DVDD2
0.1
0.1
C128
C124
C127 0.1
270
TEST2
R114
6pF
6pF
24MHz
C126
C125
P117
P118
X102
R113 220
129
130
131
138
132
133
134
135
136
137
UDP2
XVSS
UDM2
XVDD
RBIAS
TEST2
UVDD2
X24MIN
UVDD12
X24MOUT
TEST020TEST1
GP00_022GP00_123GP00_224GP00_325GP00_432GP00_533GP00_634GP00_7
AVDD519AVSS5
21
0
INT0
R101
X101
KEY0ACK
Enable DVDD2
18pF
Enable 5V
TP102
C109
32.768kHz
0.1
C108
GP00−3
GP00−2
GP00−1
GP00−0
TP103
OPEN(100u/25v)
0.1
C157
C107
AGND
10K
0.1
DVDD2
C141
DGND
R131
1
2
3
Vcc
GND
VOUT
IRC
U101
DGND
R153 5.49K(0.1%)
DGND
R151 10K
R152 10K
OVCRB
VBUSCUTB
M3TX
C123 0.1
P115
P109
P110
P111
P112
P113
P114
P116
119
120
121
122
123
124
125
126
128
127
UVSS2
GP08_5
GP08_2
GP08_3
GP08_4
GP08_6
GP08_7
GP09_0
GP09_1
DVDD12
LC786830
DVDD30XVSS1229XVDD1226X32KIN27X32KOUT28MODE
GP01_036GP01_137GP01_238GP01_3
31
35
TIRQ
18pF
S/L
EPSDA
EPSCL
IRC
CDSW1
CDSW2
C110
C111 0.1
GP00−6
IR
R132 20K
DGND
R134 2.2K R133
2.2K
7
8
6
5
WP
0.1
Vcc
DGND
SCL
SDA
A0
VSS
IC102
C142
1A12A23
4
DGND
CDRESB
CDRESB
PUIN
C121 0.1
C122 0.1
P108
117
118
114
116
115
DVSS
DVDD
GP08_0
GP08_1
DVDD12
GP01_440GP01_541GP01_645GP01_7
DVDD12
43
39
42
BEEP
DMUTEB
LM+
PWM
C112 0.1
TP104
1K
R135
5V
CAT24C256
DGND
CDBUSYB
6800pF
C138
R112 2.2K
113
0.1
C113
CDBUSYB
AFILT2
DVDD44DVSS
CDLRCK
CDLRCK
112
GP07_7
LM
SBSYI
CDBCK
CDDATA
OPCDM
CDBCK
CDDATA
OPCDM
SBSYI
220pF
C137
P107
077
22
R111
108
109
110
111
GP07_5
GP07_6
M3 SWDT
M3 SWCK
GP02_047GP02_148GP02_249GP02_350GP02_451GP02_5
46
TM
OVCRB
VBUSCUTB
TP105
TCS
GP02−2
1
2
U102
SFSYI
PWI
SFSYI
106
107
GP07_4
I2CL
TP106
R102 0
TCLK
TDIN
GP02−3
PiezoSpeaker
PWI
GP07_3
GP02−4
D101 GMA01
R136 1K
SBCKO
105
52
I2DA
TP107
0
R103
TDO
SBCKO
GP07_2
GP02−5
LM
S/L
DMUTEB
CDSW1
CDSW2
PUIN
CDDO
CDCE
CDDI
CDCL
LM+
CDDI
CDDO
CDCL
CDCE
DMUTEB
LM
S/L
CDSW1
CDSW2
PUIN
LM+
DVDD
DACDATA
DACBCK
DACLRCK
DACDATAR
DACDATAS
GP074
GP070
GP071
GP072
GP073
8
4.7K
P105
P106
R195
IC104
1DO2
8
47
GP07_1
104
R180 47
R18147R182
GP07_0
103
SFLDI2
102
SFLCL2
101
SFLHOLD2 SFLCS2 SFLDO2 SFLWP2
DVDD
DVSS
DVDD12
SFLDI1 SFLCL1 SFLHOLD1 SFLCS1 SFLDO1 SFLWP1 GP04_1 GP04_0
DVSS
DVDD
GP05_7 / AD7 GP05_6 / AD6 GP05_5 / AD5 GP05_4 / AD4
DVDD
DVSS
DVDD12
GP05_3 / AD3 GP05_2 / AD2 GP05_1 / AD1 GP05_0 / AD0 GP04_7 GP04_6 GP04_5 GP04_4 GP04_3 GP04_2 M0 SWCK M0 SWDT GP03_6 GP03_5
DVDD
DVSS
DVDD12
GP03_4 GP03_3 GP03_2 GP03_1 GP03_0 GP02_7 GP02_6
OPEN
OPEN
R104
R105
Q101
PN2222
123
IC103
100
99
47
R179 R178
98
47
97
47
R177
96
95
94
R176
93
47
R175
92
47
R174
91
47
R173
90
47
89
47
R172
88
R171 47
87 86
85
84
GP05AD7
83
GP05AD6
82
GP05AD5
81
GP05AD4
80
79
78
77
GP05AD3
76
GP05AD2
75
GP05AD1
74
GP05AD0
73
GP044
72 71
0.01
C175
70
0.01
C174
69
1K
R110
68
R108
1K
67 66
R106 22
65 64 63
62
61
60
59 58 57 56 55 54 53
TX0
RX0
RE−A
LEDCSRESET
D/C
SCK
MISO
MOSI
TP108
TP109
M0TX
GP03−0
GP03−3
GP03−6
GP03−4
GP03−5
GP03−1
GP03−2
TEST1
TEST1
TEST0
DGND
DSW101
SWDIP4
Not mounted
6
DVDD2
7 8
Figure 12. LC786830 DEMO (Main Board)
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