ON Semiconductor LC75829PE, LC75829PW Schematic

Ordering number : ENA1462

LC75829PE
LC75829PW

CMOS IC

http://onsemi.com

1/4 and 1/3-Duty General-Purpose
LCD Display Driver

Overview

The LC75829PE and LC75829PW are 1/4 duty and 1/3 duty general-purpose microprocessor-controlled LCD drivers
that can be used in applications such as frequency display in products with electronic tuning.
In addition to being able to drive up to 208 segments directly, the LC75829PE and LC75829PW can also control up
to 4 general-purpose output ports. Incorporation of an oscillation circuit helps to reduce the number of external
resistors and capacitors required.

Features

• Support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control.
When 1/4-duty: Capable of drivi ng up to 20 8 segments
When 1/3-duty: Capable of drivi ng up to 15 9 segments

• Serial data input supports CCB format communication with the system controller. (Suppo rt 3.3V and 5V operation)

• Serial data control of the power-saving mode based backup function and the all segments forced off function.

• Serial data control of switching between the segment output port and general-purpose output port function.

(Support for up to 4 general-purpose output ports)

• Support for clock output function of 1ch.

• Serial data control of the frame frequency of the common and segment output waveforms.

• Serial data control of switching between the internal oscillator operating mode and external clock operating mode.

• High generality, since display data is displayed directly without the intervention of a decoder circuit.

• The INH

• Incorporation of an oscillator circuit. (Incorporation of resistor and capacitor for an oscillation )

pin allows the display to be forced to the off state.

• CCB is ON Semiconductor® ’s original format. All addresses are managed

by ON Semiconductor® for this format.

• CCB is a registered trademark of Semiconductor Components Industries, LLC.

Semiconductor Components Industries, LLC, 2013

July, 2013

52709HKIM 20090421-S00013,20090421-S00010 No.A1462-1/22

LC75829PE, 75829PW

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0V

Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VDD max VDD
Input voltage

Output voltage V
Output current

Allowable power dissipation Pd max Ta=85°C
Operating temperature Topr
Storage temperature Tstg

VIN1 CE, CL, DI,
VIN2 OSCI, VDD1, VDD2

S1 to S53, COM1 to COM4, P1 to P4

OUT

I

1 S1 to S52

OUT

I

2 COM1 to COM4, S53

OUT

I

3 P1 to P4

OUT

INH

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V

Parameter Symbol Conditions

Supply voltage VDD VDD
Input voltage

Input high-level voltage

Input low-level voltage

External clock operating frequency fCK
External clock duty cycle DCK
Data setup time tds CL, DI [Figure 2][Figure 3]
Data hold time tdh CL, DI [Figure 2][Figure 3]
CE wait time tcp CE, CL [Figure 2][Figure 3]
CE setup time tcs CE, CL [Figure 2][Figure 3]
CE hold time tch CE, CL [Figure 2][Figure 3]
High-level clock pulse width
Low-level clock pulse width
Rise time tr CE, CL, DI [Figure 2][Figure 3]
Fall time tf CE, CL, DI [Figure 2][Figure 3]

switching time tc

INH

VDD1 VDD1
VDD2 VDD2

VIH1 CE, CL, DI,
VIH2 OSCI: External clock operating mode
VIL1 CE, CL, DI,
VIL2

tφH CL [Figure 2][Figure 3]
tφL CL [Figure 2][Figure 3]

OSCI: External clock operating mode
OSCI: External clock operating mode
OSCI: External clock operating mode

, CE [Figure 5][Figure 6]

INH

INH

INH

[Figure 4]
[Figure 4]

min typ max

4.5 6.0 V

0.4V

DD

0.4V

DD

0 0.2V

0 0.2V
10 300 600 kHz
30 50 70 %

160 ns
160 ns
160 ns
160 ns
160 ns
160 ns
160 ns

10 μs

-0.3 to +6.5 V

-0.3 to +6.5

-0.3 to VDD+0.3

-0.3 to VDD+0.3 V
300 μA

200 mW

-40 to +85 °C

-55 to +125 °C

Ratings

2/3VDD V
1/3VDD V

6.0
V

160 ns
160 ns

V

3

mA

5

DD
DD

DD
DD
DD

Unit

V

V

V

No.A1462-2/22

LC75829PE, 75829PW

SS

Electrical Characteristics for the Allowable Operating Ranges

Parameter Symbol Pin Conditions

Hysteresis VH CE, CL, DI,
Input high-level current

Input low-level current

Output high-level voltage

Output low-level voltage

Output middle-level
voltage *1

Oscillator frequency fosc Internal

Current drain

IIH1 CE, CL, DI,
IIH2 OSCI VI = VDD: External clock operating mode
IIL1 CE, CL, DI,

IIL2 OSCI VI = 0V: External clock operating mode
VOH1 S1 to S53 IO = -20μA
VOH2 COM1

to COM4

VOH3 P1 to P4 IO = -1mA
VOL1 S1 to S53 IO = 20μA
VOL2 COM1

to COM4

VOL3 P1 to P4 IO =1mA

V

1 S1 to S53 1/3 bias IO = ±20μA 2/3VDD

MID

V

2 S1 to S53 1/3 bias IO = ±20μA 1/3VDD

MID

V

3 COM1

MID

V

MID

IDD1 VDD Power-saving mode
IDD2 VDD V

IDD3 VDD V

to COM4

4 COM1

to COM4

oscillator circuit

INH

VI = 6.0V

INH

VI = 0V

INH

IO = -100μA

IO = 100μA

1/3 bias IO = ±100μA 2/3VDD

1/3 bias IO = ±100μA 1/3VDD

Internal oscillator operating mode

= 6.0V

DD

Output open
Internal oscillator operating mode

= 6.0V

DD

Output open
External clock operating mode
f

= 300kHz

CK

VIH2 = 0.5V
VIL2 = 0.1VDD

DD

min typ max

VDD-0.9

VDD-0.9

VDD-0.9

Note: *1 Excluding the bias voltage generation divider resistors built in the VDD1 and VDD2. (See Figure 1.)

V

DD

VDD1

To the common and segment drivers

VDD2

Except these resistors.

V

[Figure 1]

Ratings

0.03VDD V

5.0

5.0

-5.0

-5.0

0.9

0.9

0.9
2/3V

-0.9

-0.9

-0.9

-0.9
240 300 360 kHz

100

800 1600

800 1600

1/3V

2/3V

1/3V

DD

+0.9

DD

+0.9

DD

+0.9

DD

+0.9

Unit

μA

μA

V

V

V

μA

No.A1462-3/22

LC75829PE, 75829PW

φ

φ

1. When CL is stopped at the low level

CE

L tφH

t

tr tf

tdh

t

≈ ≈ ≈ ≈

[Figure 2]

H tφL

VIH1
50%
VIL1

≈ ≈≈≈

VIH1

VIL1

[Figure 3]

tCKL tCKH

[Figure 4]

CL

DI

VIH1

50%
VIL1

VIH1

VIL1

tr tf

tds

tdh

2. When CL is stopped at the high level

CE

CL

DI

tds

3. OSCI pin clock timing in external clock operating mode

OSCI

VIH2
50%
VIL2

VIH1

VIH1

fCK=

DCK=

1

tCKH+ tCKL

tCKH

tCKH+ tCKL

≈ ≈≈≈

[kHz]

×100[%]

≈

VIL1

≈
≈ ≈

tch tcstcp

VIL1

tch tcstcp

No.A1462-4/22

LC75829PE, 75829PW

Package Dimensions Package Dimensions

unit : mm (typ) unit : mm (typ)
3159A [LC75829PE] 3190A [LC75829PW]

49

64

116

(1.0)

(2.7)

3.0max

0.1

0.8

17.2

14.0

3348

32

14.0

17.2

17

0.35

SANYO : QIP64E(14X14)

0.15

12.0

0.8

49

64

(1.25)

(1.5)

1.7max

0.1

10.0

3348

32

12.0

10.0

17

116

0.5

0.18

0.5

0.15

SANYO : SQFP64(10X10)

Pin Assignment

S51/COM4

S53/OSCI

S49
S50

COM3
COM2
COM1

S52

VDD
VDD1
VDD2

VSS

INH

CE

CL

DI

S48

S47

S46

S44

S45

LC75829PE

LC75829PW

S42

S43

S41

S40

S39

(QIP64E)

(SQFP64)

S38

S37

S36

S35

S34

3348

32 49

S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17

17 64

161

P1/S1

P2/S2

P4/S4

P3/S3

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16 S33

Top view

No.A1462-5/22

Block Diagram

INH

S53/OSCI

VDD

VDD1

VDD2

VSS

LC75829PE, 75829PW

COM3

COM2

COM1

COMMON

DRIVER

CLOCK

GENERATOR

COM4/S51

CONTROL

REGISTER

CCB INTERFACE

DI

S4/P4

S52

S50

SEGMENT DRIVER & LATCH

SHIFT REGISTER

CL

CE

S5

S2/P2

S3/P3

S1/P1

No.A1462-6/22

LC75829PE, 75829PW

Pin Functions

Symbol Pin No. Function Active I/O

S1/P1 to S4/P4

S5 to S50

S52

1 to 4

5 to 50

55

Segment outputs for displaying the display data transferred by serial data input.
The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial
data control.

Handling

when

unused

- O OPEN

COM1 to COM3

COM4/S51

S53/OSCI 60

CE 62 H I

CL 63

DI 64

INH

VDD1 57
VDD2 58

VDD 56

VSS 59

54 to 52

51

61

Common driver outputs
The frame frequency is fo[Hz].
The COM4/S51 pin can be used as a segment output in 1/3 duty.
Segment output. This pin can also be used as the external clock input pin when the
external clock operating mode is selected by control data.
Serial data transfer inputs. Must be connected to the controller.

CE: Chip enable
CL: Synchronization clock
DI: Transfer data

Display off control input

•

= low (VSS) ...Display forced off

INH

S1/P1 to S4/P4 = low (VSS)
(These pins are forcibly set to the general-purpose output port
function and held at the VSS level.)
S9 to S50, S52=low (VSS)
COM1 to COM3=low (VSS)
COM4/S51=low (VSS)
S53/OSCI=low (VSS)
(This pin is forcibly set to the segment output port function and
held at the VSS level.)
Stops the internal oscillator.
Inhibits external clock input.

•

= high (VDD)...Display on

INH

Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)

However, serial data transfer is possible when the display is forced off.
Used to apply the LCD drive 2/3 bias voltage externally.
Used to apply the LCD drive 1/3 bias voltage externally.
Power supply pin. A power voltage of 4.5 to 6.0V must be applied to this pin.
Ground pin. Must be connected to ground.

- O OPEN

- I/O OPEN

I GND

- I

L I GND

- I OPEN

- I OPEN

- - -

- - -

No.A1462-7/22