ON Semiconductor KAC-12040 User Manual
KAC-12040
f
4000 (H) x 3000 (V)
CMOS Image Sensor
Description
The KAC−12040 Image Sensor is a high-speed 12 megapixel
CMOS image sensor in a 4/3″ optical format based on a 4.7 mm 5T
CMOS platform. The image sensor features very fast frame rate,
excellent NIR sensitivity, and flexible readout modes with multiple
regions of interest (ROI). The readout architecture enables use of 8, 4,
or 2 LVDS output banks for full resolution readout of 70 frames per
second.
Each LVDS output bank consists of up to 8 differential pairs
operating at 160 MHz DDR for a 320 Mbps data rate per pair.
The pixel architecture allows rolling shutter operation for motion
capture with optimized dynamic range or global shutter for precise
still image capture.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture 5T Global Shutter CMOS
Resolution 12 Megapixels
Aspect Ratio 4:3
Pixel Size
Total Number of Pixels 4224 (H) × 3192 (V)
Number of Effective Pixels 4016 (H) × 3016 (V)
Number of Active Pixels 4000 (H) × 3000 (V)
Active Image Size 18.8 mm (H) × 14.1 mm (V)
Master Clock Input Speed 5 MHz to 50 MHZ
Maximum Pixel Clock Speed 160 MHz DDR LVDS, 320 Mbps
Number of LVDS Outputs 64 Differential Pairs
Number of Output Banks 8, 4, or 2
Frame Rate, 12 Mp 1−70 fps 10 bits
Charge Capacity 16,000 electrons
Quantum Efficiency
KAC−12040−CBA
KAC−12040−ABA
Read Noise
(at Maximum LVDS Clock)
Dynamic Range 73 dB, Rolling Shutter
Blooming Suppression > 10,000x
Image Lag 1.3 electron
Digital Core Supply 2.0 V
Analog Core Supply 1.8 V
Pixel Supply 2.8 V & 3.5 V
Power Consumption 1.5 W for 12 Mp @ 70 fps 10 bits
Package 267 Pin Ceramic Micro-PGA
Cover Glass AR Coated, 2-sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
4.7 mm (H) × 4.7 mm (V)
23.5 mm (Diagonal), 4/3″ Optical Format
1−75 fps 8 bits
40%, 47%, 45% (470, 540, 620 nm)
53%, 15%, 10% (500, 850, 900 nm)
3.7 e− rms, Rolling Shutter
−
25.5 e
rms, Global Shutter
56 dB, Global Shutter
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Figure 1. KAC−12040 CMOS Image Sensor
Features
• Global Shutter and Rolling Shutter
• Very Fast Frame Rate
• High NIR Sensitivity
• Multiple Regions of Interest
• Interspersed Video Streams
Applications
• Machine Vision
• Intelligent Transportation Systems
• Surveillance
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 o
this data sheet.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 5
1 Publication Order Number:
KAC−12040/D
KAC−12040
The image sensor has a pre-configured QFHD (4 × 1080p,
16:9) video mode, fully programmable, multiple ROI for
windowing, programmable sub-sampling, and reverse
readout (flip and mirror). The two ADCs can be configured
clamping, overflow pixel for blooming reduction, black-sun
correction (anti-eclipse), column and row noise correction,
and integrated timing generation with SPI control, 4:1 and
9:1 averaging decimation modes.
for 8-bit, 10-bit, 12-bit or 14-bit conversion and output.
Additional features include interspersed video streams
(dual-video), on-chip responsivity calibration, black
ORDERING INFORMATION
T able 2. ORDERING INFORMATION − KAC−12040 IMAGE SENSOR
Part Number Description Marking Code
KAC−12040−ABA−JD−BA Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR
KAC−12040−ABA−JD−AE Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR
KAC−12040−CBA−JD−BA Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover
KAC−12040−CBA−JD−AE Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover
1. Engineering Grade samples might not meet final production testing limits, especially for cosmetic defects such as clusters, but also possibly
column and row artifacts. Overall performance is representative of final production parts.
Coating (Both Sides), Standard Grade.
Coating (Both Sides), Engineering Grade.
Glass with AR Coating (Both Sides), Standard Grade.
Glass with AR Coating (Both Sides), Engineering Grade.
KAC−12040−ABA
Serial Number
KAC−12040−CBA
Serial Number
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAC−12040−CB−A−GEVK Evaluation Hardware for KAC−12040 Image Sensor (Color). Includes Image Sensor.
KAC−12040−AB−A−GEVK Evaluation Hardware for KAC−12040 Image Sensor (Monochrome). Includes Image Sensor.
LENS−MOUNT−KIT−C−GEVK Lens Mount Kit that Supports C, CS, and F Mount Lenses. Includes IR Cut-filter for Color Imaging.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com
.
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DEVICE DESCRIPTION
Architecture
KAC−12040
1D
0D
− 1D
0
− 0D
0
Clk1
Clk0
6
− 5D
0
5D
Clk7
Clk3
6
− 3D
0
3D
Clk5
LVDS Bank 3 LVDS Bank 5 LVDS Bank 7
Odd Row ADC, Analog Gain, Black-Sun Correction
88
6
B
G
R
G
8
B
G
4000 (H) y 3000 (V)
6
− 7D
0
7D
3.5 V
A
3.3 V
D
2.8 V
A
2.0 V
D
1.8 V
A
G
R
Chip Clock (2 Pins)
TRIGGER
RESETN
4.7 mm Pixel
104
8
8
104
CSN
SCLK
MOSI
6
Digital Gain/Offset, Noise Correction
LVDS Bank 0 LVDS Bank 1
(0, 0)
B
G
R
G
8
88
B
G
R
G
Timing Control, Sub-Sampling/Averaging
Even Row ADC, Analog Gain, Black-Sun Correction
MISO
ADC_Ref1
4.02 kW ±1%
ADC_Ref2
Serial
Peripheral
Interface
(SPI)
LVDS Bank 2 LVDS Bank 4 LVDS Bank 6
VSS 0 V
Clk2
6
− 2D
0
2D
6
Clk4
− 4D
0
4D
Figure 2. Block Diagram
Clk6
6
− 6D
0
6D
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Physical Orientation
272625242322212019181716151413121110987654321
KAC−12040
A
B
C
D
E
LVDS Bank 3 LVDS Bank 5 LVDS Bank 7
LVDS Bank 0 LVDS Bank 1
LVDS Bank 2 LVDS Bank 4 LVDS Bank 6
Notes:
1. The center of the pixel array is aligned to the physical package center.
2. The region under the sensor die is clear of pins enabling the use of a heat sink.
3. Non-symmetric mounting holes provide orientation and mounting precision.
4. Non-symmetric pins prevent incorrect placement in PCB.
5. Letter “F” indicator shows default readout direction relative to package pin 1.
Figure 3. Package Pin Orientation − Top X-Ray View
AA
AB
AC
AD
AE
272625242322212019181716151413121110987654321
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KAC−12040
Table 4. PRIMARY PIN DESCRIPTION
Pin Name Type Description
AB09 RESETN DI Sensor Reset (0 V = Reset State)
E07 CLK_In1 DI Sensor Input Clk_In1 (45−50 MHz)
D08 CLK_In2 DI Sensor Input Clk_In2 (Connect to Clk1)
AB08 TRIGGER DI Trigger Input (Optional)
AA05 SCLK DI SPI Master Clock
AA08 MOSI DI SPI Master Output, Slave Input
AA07 MISO DO SPI Master Input, Slave Output
AA06 CSN DI SPI Chip Select (0 V = Selected)
AA14 ADC_Ref1 AO
AA15 ADC_Ref2 AO
AB07 MSO DO Mechanical Shutter Output Sync (Optional)
AB06 FLO DO Flash Output Sync (Optional)
E05 FEN DO Frame Enable Reference Output (Optional)
E06 LEN DO Line Enable Reference Output (Optional)
1. DI = Digital Input, DO = Digital Output, AO = Analog Output.
2. Tie unused DI pins to Ground, NC unused DO pins.
3. By default Clk_In2 should equal Clk_In1 and should be the same source clock.
4. The RESETN pin has a 62 kW internal pull-up resistor, so if left floating the chip will not be in reset mode.
5. The TRIGGER pin has an internal 100 kW pull down resistor. If left floating (and at default polarity) then the sensor state will not be affected
by this pin (i.e. defaults to ‘not triggered’ mode if floated).
6. All of the DI and DO pins nominally operate at 0 V → 2.0 V and are associated with the VDD_DIG power supply.
4.02 kW ±1% Resistor between Ref1 & Ref2
4.02 kW ±1% Resistor between Ref1 & Ref2
Table 5. POWER PIN DESCRIPTION
Name Voltage Pins Description
VDD_LVDS 3.3 V D C04, C05, C23, C24, D04, D24, E04, E24, AA04, AA24,
AB04, AB24, AC04, AC05 AC23, AC24
VDD_DIG 2.0 V D C18, C19, D18, D19, E18, AA18, AB18, AB19, AC18, AC19,
C20, C21, C22, D20, D21, D22, D23, E20, E21, E22, AA20,
AA21, AA22, AB20, AB21, AB22, AB23, AC20, AC21,
AC22, AB15, E08
AVDD_HV 3.5 V A C11, D11, E11, AA11, AB11, AC11, C10, D10, E10, AA10,
AB10, AC10
Vref_P 2.8 V A C13, D13, E13, AA13, AB13, AC13 Pixel Supply 2
AVDD_LV 1.8 V A C17, D16, D17, E17, AA17, AB16, AB17, AC17 Analog Low Voltage Supply
Vpixel_low 0 V E09 Pixel Supply 3. Combine with VSS for
VSS 0 V C12, C14, D12, D14, E12, AA12, AB12, AB14, AC12, AC14,
E15, D15, AA09, A02, A14, A26, B14, C03, C06, C25, D03,
D25, E03, E19, E23, E25, AA03, AA19, AA23, AA25, AB25,
AC03, AC06, AC25, AD14, AE02, AE14, AE26
No Connect NA A01, AC09, E14, E16, C09, D09, D05, D06, D07, AA16,
AB05
LVDS Output Supply
Digital Core Supply
Pixel Supply 1
normal operation. Can be pulsed for
Extended Dynamic Range Operation.
Sensor Ground Reference
Unused and test-only pins. These
pins must be floated.
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Table 6. L VDS PIN DESCRIPTION
KAC−12040
Pin Name Description
E01
1DCLK+
E02 1DCLK−
D01 1DATA0+
D02 1DATA0−
C01 1DATA1+
C02 1DATA1−
B01 1DATA2+
B02 1DATA2−
A03 1DATA3+
B03 1DATA3−
A04 1DATA4+
B04 1DATA4−
A05 1DATA5+
B05 1DATA5−
A06 1DATA6+
B06 1DATA6−
Pin Name Description
0DCLK+
AA01
AA02 0DCLK−
AB01 0DATA0+
AB02 0DATA0−
AC01 0DATA1+
AC02 0DATA1−
AD01 0DATA2+
AD02 0DATA2−
AE03 0DATA3+
AD03 0DATA3−
AE04 0DATA4+
AD04 0DATA4−
AE05 0DATA5+
AD05 0DATA5−
AE06 0DATA6+
AD06 0DATA6−
Bank 1
LVDS Clock
Bank 1
LVDS Data
Bank 0
LVDS Clock
Bank 0
LVDS Data
Pin Name Description
C07
3DCLK+
C08 3DCLK−
A07 3DATA0+
B07 3DATA0−
A08 3DATA1+
B08 3DATA1−
A09 3DATA2+
B09 3DATA2−
A10 3DATA3+
B10 3DATA3−
A11 3DATA4+
B11 3DATA4−
A12 3DATA5+
B12 3DATA5−
A13 3DATA6+
B13 3DATA6−
Pin Name Description
2DCLK+
AC07
AC08 2DCLK−
AE07 2DATA0+
AD07 2DATA0−
AE08 2DATA1+
AD08 2DATA1−
AE09 2DATA2+
AD09 2DATA2−
AE10 2DATA3+
AD10 2DATA3−
AE11 2DATA4+
AD11 2DATA4−
AE12 2DATA5+
AD12 2DATA5−
AE13 2DATA6+
AD13 2DATA6−
Bank 3
LVDS Clock
Bank 3
LVDS Data
Bank 2
LVDS Clock
Bank 2
LVDS Data
Pin Name Description
C15
5DCLK+
C16 5DCLK−
A15 5DATA0+
B15 5DATA0−
A16 5DATA1+
B16 5DATA1−
A17 5DATA2+
B17 5DATA2−
A18 5DATA3+
B18 5DATA3−
A19 5DATA4+
B19 5DATA4−
A20 5DATA5+
B20 5DATA5−
A21 5DATA6+
B21 5DATA6−
Pin Name Description
4DCLK+
AC15
AC16 4DCLK−
AE15 4DATA0+
AD15 4DATA0−
AE16 4DATA1+
AD16 4DATA1−
AE17 4DATA2+
AD17 4DATA2−
AE18 4DATA3+
AD18 4DATA3−
AE19 4DATA4+
AD19 4DATA4−
AE20 4DATA5+
AD20 4DATA5−
AE21 4DATA6+
AD21 4DATA6−
Bank 5
LVDS Clock
Bank 5
LVDS Data
Bank 4
LVDS Clock
Bank 4
LVDS Data
Pin Name Description
A22
7DCLK+
B22 7DCLK−
A23 7DATA0+
B23 7DATA0−
A24 7DATA1+
B24 7DATA1−
A25 7DATA2+
B25 7DATA2−
B27 7DATA3+
B26 7DATA3−
C27 7DATA4+
C26 7DATA4−
D27 7DATA5+
D26 7DATA5−
E27 7DATA6+
E26 7DATA6−
Pin Name Description
6DCLK+
AE22
AD22 6DCLK−
AE23 6DATA0+
AD23 6DATA0−
AE24 6DATA1+
AD24 6DATA1−
AE25 6DATA2+
AD25 6DATA2−
AD26 6DATA3+
AD27 6DATA3−
AC26 6DATA4+
AC27 6DATA4−
AB26 6DATA5+
AB27 6DATA5−
AA26 6DATA6+
AA27 6DATA6−
Bank 7
LVDS Clock
Bank 7
LVDS Data
Bank 6
LVDS Clock
Bank 6
LVDS Data
1. All LVDS Data and Clock lines must be routed with 100 W differential transmission line traces.
2. All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data lines.
3. In 2 Bank mode, only LVDS banks 0 and 1 are active.
4. In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active.
5. Float the pins of unused LVDS Banks to conserve power.
6. Unused pins in active banks (due to ADC bit depth < 14) are automatically tri-stated to save power, but these can also be floated.
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KAC−12040
IMAGING PERFORMANCE
Table 7. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description
Light Source Continuous Red, Green and Blue LED Illumination 1
Temperature Measured Die Temperature: 40°C and 27°C
Integration Time 16.6 ms (1400d LL, Register 0201h)
Readout Mode Dual-Scan, Global Shutter, 320 MHz, PLL2
Clamps Column/Row Noise Corrections Active, Frame Black Level Clamp Active
ADC Bit Depth 10 bit
Analog Gain Unity Gain or Referred Back to Unit Gain
1. For monochrome sensor, only green LED used.
T able 8. KAC−12040−ABA CONFIGURATION (MONOCHROME)
Wavelength
Description Symbol
Peak Quantum Efficiency
Green
NIR1
NIR2
Responsivity − 84 −
Responsivity − 7.0 −
QE
MAX
(nm)
550
850
900
Condition Notes
Temperature
Min. Nom. Max. Unit
−
−
−
53
15
10
−
−
−
% Design 27
ke
Lux @ s
V
Lux @ s
*
Sampling
Plan
Design 27 20
Design 27 21
Tested at
(5C)
Test
T able 9. KAC−12040−CBA CONFIGURATION (BAYER RGB)
Wavelength
Description Symbol
Peak Quantum Efficiency
Green
NIR1
NIR2
Responsivity Blue
Responsivity Blue
QE
MAX
(nm)
470
540
620
850
900
Green
Red
Green
Red
Min. Nom. Max. Unit
−
−
−
−
−
−
−
−
−
−
−
40
47
45
15
10
17
35
38
1.4
2.9
3.2
Sampling
Plan
−
−
−
−
−
−
−
−
−
−
−
% Design 27
*
ke
Lux @ s
V
Lux @ s
Design 27 20
Design 27 21
Temperature
Tested at
(5C)
Test
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KAC−12040
Table 10. PERFORMANCE SPECIFICATIONS ALL CONFIGURATIONS
Description Symbol Min. Nom. Max. Unit
Photodiode Charge
Capacity
PNe − 16 − ke
−
Sampling
Plan
Tested at
(5C)
Die 27, 40 16
Temperature
Test Notes
Read Noise ne−T −
Total Pixelized Noise −
Dynamic Range DR −
Column Noise C
Row Noise R
Dark Field Local
N
N
DSNU_flr −
Non-Uniformity Floor
Bright Field Global
PRNU_1 − 1.5 − % rms Die 27, 40 2 2
3.7 RS
−
25.5 GS
4.5 RS
−
28.3 GS
73 RS
−
56 GS
−
0.6 RS
−
3.0 GS
−
1.0 RS
−
5.0 GS
3.0 RS
−
21 GS
−
e− rms Die 27 8 1
−
−
e− rms Die 27 19 1
−
−
dB Die 27 1, 4
−
−
e− rms Die 27 9 1, 6
−
−
e− rms Die 27 10 1, 7
−
−
e− rms Die 27, 40 1 1, 5
−
Photoresponse
Non-Uniformity
Bright Field Global Peak to
PRNU_2 − 6.5 − % pp Die 27, 40 3 2
Peak Photoresponse
Non-Uniformity
Maximum Photoresponse
NL − 6.3 − % Die 27, 40 11 3
Non-Linearity
Maximum Gain Difference
DG
− 0.3 − % Die 27, 40 12 8
between Outputs
Photodiode Dark Current I
Storage Node Dark Current I
PD
VD
Image Lag Lag − 1.3 10
Black-Sun Anti-Blooming X
AB
− 4.6 70 e/p/s Die 40 13 9
− 1,200 5,000 e/p/s Die 40 14 5
−
−
−
12
> 10,000
−
W/cm
−
xllumSat
Design 27, 40 15
2
Design 27 7 14
Parasitic Light Sensitivity PLS − 730 − − Design 27 6 10
Dual-Video WDR −
Pulsed Pixel WDR
140 RS
−
120 GS
−
dB Design 27 1, 11,
−
− 100 − dB Design 27 12, 13
(GS Only)
1. RS = Rolling Shutter Operation Mode, GS = Global Shutter Operation Mode.
2. Measured per color, worst of all colors reported.
3. Value is over the range of 10% to 90% of photodiode saturation, Green response used.
4. Uses 20LOG (PNe / ne
−
T).
5. Photodiode dark current made negligible.
6. Column Noise Correction active.
7. Row Noise Correction active.
8. Measured at ~70% illumination.
9. Storage node dark current made negligible.
10.GSE (Global Shutter Efficiency) = 1 −1 / PLS.
11.Min vs Max integration time at 30 fps.
12.WDR measures expanded exposure latitude from linear mode DR.
13.Min/Max responsivity in a 30 fps image.
14.Saturation Illumination referenced to a 3 line time integration.
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TYPICAL PERFORMANCE CURVES
KAC−12040
Figure 4. Monochrome QE (with Microlens)
Figure 5. Bayer QE (with Microlens)
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KAC−12040
Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied along the wider array dimension.
For the curves marked “Vertical”, the incident light angle is varied along the shorter array dimension.
Figure 6. Monochrome Relative Angular QE (with Microlens)
Figure 7. Bayer Relative Angular QE (with Microlens)
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Dark Current vs. Temperature
NOTE: “Dbl” denotes an approximate doubling temperature for the dark current for the displayed temperature range.
KAC−12040
Figure 8. Dark Current vs. Temperature
Power vs. Frame Rate
The most effective method to use the maximum PLL2
speed (313 → 320 MHz) and control frame rate with
minimum Power and maximum image quality is to adjust
Vertical Blanking. (register 01F1h). Unnecessary chip
operations are suspended during Vertical Blanking
conserving significant power consumption and also
minimizing the image storage time on the storage node when
in Global Shutter Operation.
NOTE: The LVDS clock is ½ the PLL2 clock speed.
Figure 9. Power vs. Frame Rate, 10 bit Mode
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KAC−12040
Power and Frame Rate vs. ADC Bit Depth
Increasing the ADC bit depth impacts the frame rate by
changing the ADC conversion time. The following figure
shows the power and Frame rate range for several typical
cases.
Figure 10. ADC Bit Depth Impact on Frame Rate and Power
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KAC−12040
DEFECT DEFINITIONS
Table 11. OPERATION CONDITIONS FOR DEFECT TESTING
Description Condition Notes
Operational Mode 10 bit ADC, 8 LVDS Outputs, Global Shutter and Rolling Shutter Modes,
Pixels per Line 4,000
Lines per Frame 3,000
Line Time
Frame Time 13.9 ms
Photodiode Integration Time 33 ms
Storage Readout Time 13.9 ms
Temperature 40°C and 29°C
Light Source Continuous Red, Green and Blue LED Illumination 1
Operation Nominal Operating Voltages and Timing, PLL1 = 320 MHz, Wafer Test
1. For monochrome sensor, only the green LED is used.
Table 12. DEFECT DEFINITIONS FOR TESTING
Description Definition Limit Test Notes
Dark Field Defective Pixel 30°C
Bright Field Defective Pixel Defect ≥ ±12% from Local Mean 120 5 2, 5
Cluster Defect A group of 2 to 10 contiguous defective pixels, but
Column/Row Major Defect A group of more than 10 contiguous defective pixels
Dark Field Faint Column/Row Defect RS: 3 dn Threshold
Bright Field Faint Column/Row Defect RS: 12 dn Threshold
1. RS = Rolling Shutter, GS = Global Shutter.
2. For the color devices, all bright defects are defined within a single color plane, each color plane is tested.
3. Cluster defects are separated by no less than two good pixels in any direction.
4. Rolling Shutter Dark Field points are dominated by photodiode integration time, Global Shutter Dark Field defects are dominated by the
readout time.
5. The net sum of all bright and dark field pixel defects in rolling and global shutter are combined and then compared to the test limit.
Dual-Scan, Black Level Clamp ON, Column/Row Noise Corrections ON,
1× Analog Gain, 1× Digital Gain
8.7 ms
RS: Defect ≥ 20 dn
GS: Defect ≥ 180 dn
no more than 3 adjacent defects horizontally.
along a single column or row.
GS: 10 dn Threshold
GS: 18 dn Threshold
40°C
RS: Defect ≥ 30 dn
GS: Defect ≥ 240 dn
120 4 1, 4, 5
22 3
0
0 17 1
0 18 1
Defect Map
The defect map supplied with each sensor is based upon
testing at an ambient (29°C) temperature. All defective
pixels are reference to pixel (0, 0) in the defect maps. See
Figure 11 for the location of pixel (0, 0).
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