ON Semiconductor FUSB307B User manual

FUSB307B

USB Type-C Port Controller with USB-PD

Description

The FUSB307B targets system designers looking to implement up to four USB Type−C port controllers (TCPC) with USB−PD capabilities.

This solution provides integrated Type−C Rev 1.3 detection circuitry enabling manual attach/detach detection. Time critical Power Delivery functionality is handled autonomously, offloading the μProcessor or Type−C Port Manager (TCPM).

The FUSB307B complies with the USB−PD Interface Specification Rev 1.0 as a TCPC for a standardized interface with TCPM.

Features

• USB−PD Interface Specification Rev 1.0 Ver. 1.2 Compatible

• USB Type−C Rev 1.3 Compatible

• USB−PD Rev3.0 Ver. 1.1 Compatible

• Fast Role Swap

• Sink Transmit

• Extended Data Messages (Chunked)

• Dual−Role Functionality

♦ Manual Type−C Detection ♦ Automatic DRP Toggling

• USB−PD Interface Specification Support

♦ Automatic GoodCRC Packet Response ♦ Automatic Retries of Sending Packet ♦ All SOP* Types Supported

• VBUS Source and Sink Control

• Integrated 3 W Capable VCONN to CCx Switch

• 10−bit VBUS ADC

• Programmable GPIOs

• 4 Selectable I

C Addresses

www.onsemi.com

SCALE 3:1

WQFN16 3 x 3, 0.5P

CASE 510BS

PIN ASSIGNMENT

GPIO1

1 CC1

VCONN

3 CC2

ORIENT

LDO

GND

Top Through

View

GND

VBUS

QFN16

SNK

VDD

SRC

12 SDA1

11 SCL1

10 INT_N

9 GPIO2

DBG_N

ORDERING INFORMATION

See detailed ordering and shipping information on page 3 o this data sheet.

eatures (continued)

• Dead Battery Operation

♦ Powered from VBUS ♦ LDO Output Provides Power to TCPM

• Packaging:

♦ FUSB307B− 16 Pin QFN

pplications

• Smartphones and Tablets

• Digital Cameras

• Desktops and Laptops

• Rechargeable Docks/Speakers

• Wall Adapters

Figure 1. FUSB307B Block Diagram

April, 2018 − Rev. 3

1 Publication Order Number:

• Automotive

FUSB307B/D

FUSB307B

Table of Contents

Description 1.............................................................................................

Features 1................................................................................................

Applications 1.............................................................................................

Typical Application 3.......................................................................................

Block Diagram 4..........................................................................................

Pin Configurations 4.......................................................................................

Pin Descriptions 5.........................................................................................

Power Up, Initialization and Reset 5..........................................................................

Dead Battery Power−up 6..................................................................................

Programmable GPIOx 6....................................................................................

Standard Outputs 6........................................................................................

C Interface 7............................................................................................

C Address Selection 7....................................................................................

Interrupt Operation 7.......................................................................................

C Idle Mode 7...........................................................................................

VCONN Control 7.........................................................................................

Debug Accessory Support 8................................................................................

Type−C Manual Mode Detection 8...........................................................................

BMC Power Delivery 10....................................................................................

Transmit State Machine 11..................................................................................

Hard Reset/ Cable Reset State Machine 12...................................................................

Automatic GoodCRC Response 12..........................................................................

BIST Mode 12............................................................................................

VBUS Source and Sink Control 12...........................................................................

Voltage Transitions 13......................................................................................

VBUS Monitoring and Measurement 15.......................................................................

VBUS Discharge 15.......................................................................................

Automatic Source Discharge after a Disconnect 15.............................................................

Automatic Sink Discharge after a Disconnect 16...............................................................

Sink Discharge during a Connection 17.......................................................................

Watchdog T imer 17........................................................................................

USB−PD Rev 3.0 Features 18...............................................................................

Fast Role Swap 18........................................................................................

Fast Role Swap Cable Disconnect (Informational Only) 19......................................................

DC and Transient Characteristics 21.........................................................................

www.onsemi.com

FUSB307B

Table 1. ORDERING INFORMATION

Operating

Part Number

FUSB307BMPX −40 to 85°C

FUSB307BVMPX Automotive

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

Typical Application

1 μF 25 V

Type−C

receptacle

Temperature Range

−40 to 105°C

FPF2895

30 mΩ

OUT

220 pF

ISET

FPF2895

30 mΩ

SNK

SRC GPO1 GPO2

VBUS CC1

CC2

GND

Package Packing Method†

16–Lead Molded Leadless Package (QFN) JEDEC, ML220, 3 mm Square

10 μF

OUT

10 μF

25 V

VDD

1 μF

VCONN

FUSB307B

I2C_ADDR_SEL/

ORIENT

LDO

INT_N

SDA

SCL

DEBUG_N

10 μF

VSRC V3P3

VCONN VSNK

Tape and Reel

USB Buck/Boost

+ VBUS Buck

+ VCONN Buck

1 μF

VBAT

Charger

VDD

TCPM

Battery

FUSB340

2:1 USB3.1 Switch

Figure 2. FUSB307B Typical Mobile Computing Application

USB

2.0 &

3.1

Gen1

PHY

GPU

www.onsemi.com

Block Diagram

FUSB307B

INT_N

SDA1/SCL2

SCL1/SDA2

SRC

Sink/Source

Control

I2C

SNK

Clock

Gen.

USB

FSM

10−bit

ADC

ORIENT

Discharge

Bleed Discharge Discharge

CRC32

ADDR/

DEBUG_N

VBUS

4B5B

USB PD PHY

BMC

4B5B

Dec.

GPIO Control

BMC Enc.

CDR

GPIO2/

FR_SWAP

VDD

PWR

MGMT

GPIO1

Driver

BMC

3.3V LDO

Rcvr

BMC

FUSB307B

Prog Pull−

Up Current

CC Switch/

Sense

Type−C Control

LDO

VCONN

CC1 CC2

GND

Pin Configurations

ORIENT

3 CC2

VCONN

1 CC1

Figure 3. FUSB307B Block Diagram

LDO

VBUS

VDD

DBG_N

9 GPIO2

DBG_N

Bottom View Top Through

10 INT_N

11 SCL1

12 SDA1

SRC

GPIO1

GND

10 INT_N

11 SCL1

12 SDA1

SNK

SRC

Figure 4. Pin Assignment QFN (FUSB307B)

VDD

View

GND

SNK

VBUS

GND

LDO

GPIO1

ORIENT

3 CC2

VCONN

1 CC1

www.onsemi.com

Pin Descriptions

Table 2. PIN DESCRIPTION

Name Type Description

USB TYPE−C CONNECTOR INTERFACE

FUSB307B

CC1 I/O

CC2 I/O

GND Ground Ground

VBUS Power VBUS supply pin for attach and detach detection when operating as an upstream

POWER INTERFACE

VDD Power Input supply voltage

LDO LDO Output 3.3 V LDO Output

VCONN Power Switch Regulated input to be switched to correct CC pin as VCONN to power USB3.1

SIGNAL INTERFACE

SCL1/SDA2 (Note 1) Open−Drain I/O I2C serial clock/data signal to be connected to the I2C master SDA1/SCL2 (Note 1) Open−Drain I/O I2C serial clock/data signal to be connected to the I2C master

INT_N Open−Drain Output Active LOW open drain interrupt output used to prompt the processor to read the

ORIENT/I2C_

ADDR

(Note 1)

DBG_N Open−Drain I/O Debug Accessory Detection Open−Drain Output

GPIO2 3−State CMOS I/O General Purpose I/O 2 GPIO1 3−State CMOS I/O General Purpose I/O 1

VBUS SOURCE AND SINK INTERFACE

SNK CMOS Output Controls external VBUS Sink Load Switch on/off (Active High)

SRC CMOS Output Controls external VBUS Source Load Switch on/off (Active High)

1. A different I2C address is used depending on which SDA and SCL are used and the state of ORIENT/I2C_ADDR at power up.

3−State CMOS Output Selects I2C Address on Power up and then becomes a General Purpose CMOS

Type−C connector Configuration Channel (CC) pins. Initially used to determine when an attach has occurred and what the orientation of the insertion is. Function ality after attach depends on mode of operation detected.

Operating as a host:

− Sets the allowable charging current for VBUS to be sensed by the attached device

− Used to communicate with devices using USB BMC Power Delivery

− Used to detect when a detach has occurred Operating as a device:

− Indicates what the allowable sink current is from the attached host

− Used to communicate with devices using USB BMC Power Delivery

facing port (Device)

fully featured cables, powered accessories or dongles bridging Type C to other video or audio connectors

C register bits

Output

Power Up, Initialization and Reset

When power is first applied to VDD or VBUS, the FUSB307B goes through its POR sequence to load up all the default values in the register map, read all the fuses so that the trimmed values are available when VDD or VBUS is in its valid range. A software reset can be executed by writing SW_RES to 1 in RESET Register. This executes a full reset of the FUSB307B similar to POR where all the I2C registers go to their default state.

When powered down, the FUSB307B is configured as a UFP with CC1 and CC2 have their respective Rd

www.onsemi.com

pull−downs enabled such that a SOURCE can detect this as a UFP and turn on VBUS.

For the FUSB307B device, power may become available from VBUS when VDD is not present. This state is still considered “Dead Battery” until VDD is present. During Dead Battery, the FUSB307B will continue presenting Rd.

Once VDD is available, the TCPM can start the DRP toggle by setting COMMAND.LOOK4CON on the FUSB307B device.

FUSB307B

Dead Battery Power−up

During a dead battery condition in a mobile application, the FUSB307B will be powered by VBUS and provide an LDO output to power a μController or TCPM to establish a USB−PD contract.

The FUSB307B will enable the Sink Path when attached to a source with any advertised current.

TYPE−C Port 1

1− FUSB307B

Powers from

VBUS

and attaches as

SNK

TYPE−C Port 2

3− Enable Sink

VBUS

FPF2895

30 mΩ

Path

PWR MGMT

FUSB307B

FPF2895

30 mΩ

SNK

PWR MGMT

SNK

OUT

VDD

LDO Bypass

3.3V LDO

LDO

LDO Bypass

3.3 V LDO

LDO

Systems with more than one Type−C port, the TCPM can

enable or disable the appropriate sink paths.

Once VDD is greater than V

DDGOOD

, the internal LDO is bypassed and the device switches from VBUS to VDD power.

Figure 5 demonstrates a dead battery power up sequence

for FUSB307B.

VSYS

VIN

Charger IC

6− FUSB307B

switches to

VDD Power and

bypasses LDO

5− Power to

system is

enabled

2− FUSB307B Provides Power

to EC during Dead Battery

VDD

TCPM

4− TCPM

establishes PD

Contract with

SRC

3.3 V Buck Converter

V3P3A

Battery

FUSB307B

Figure 5. FUSB307B Dead Battery Operation

Programmable GPIOx

The FUSB307B has two programmable GPIOs. These can be programmed to be Inputs, CMOS Outputs or Open Drain Outputs. To configure them, the TCPM writes to GPIO1_CFG and GPIO2_CFG. If the GPIO is configured as an input, its logic value can be read in GPIO_STAT and ALERT_VD registers.

Standard Outputs

The FUSB307B implements Orientation and supports Debug Accessory detection output as indicated in STD_OUT_CAP register.

To configure the Orientation, Mux selection, and Debug Accessory, the TCPM writes to STD_OUT_CFG.

www.onsemi.com

FUSB307B

I2C Interface

The FUSB307B includes a full I

C slave controller. The

I2C slave fully complies with the I2C specification version

6 requirements. This block is designed for fast mode plus signals.

Examples of a n I

C write and read sequence are shown in

Figure 7 and Figure 8 respectively.

8bits 8bits 8bits

Slave Address

NOTE: Single Byte read is initiated by Master with P immediately following first data byte.

8bits 8bits 8bits

S WR A A S RD A A A NA P

Slave Address

NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red

bracket is needed.

WR A

From Master to Slave S Start Condition NA NOT Acknowledge (SDA High) RD Read =1 From Slave to Master A Acknowledge (SDA Low) WR Write = 0 P

AA A A

Write Data K+2

Figure 6. I2C Write Example

8bits

Read Data K+1 Read Data K+N−1

(Single Byte read is initiated by Master with NA immediately following first data byte)

Single or multi byte read executed from current register location

Stop Condition

Figure 7. I2C Read Example

A P

I2C Address Selection

I2C Slave addresses can be changed by configuring the I2C_ADDR_GPO input on power up with a pull−up or pull−down resistor and routing the SCL and SDA lines according to Table 3.

set to 1b (due to ALERTL.I_PORT_PWR and PWRSTAT.TCPC_INIT).

When an interruptible event occurs, INT_N is driven low and is high−Z again when the processor clears the interrupt by writing a 1 to the corresponding interrupt bit position. Writing a 0 to an interrupt bit has no effect.

Interrupt Operation

The INT_N pin is an active low, open drain output which indicates to the host processor that an interrupt has occurred in the FUSB307B which needs attention. The INT_N pin is

A processor firmware has additional control of INT_N through individual event mask bits which can be set or cleared to enable or disable INT_N from being driven low when each event occurs.

asserted after power−up or device reset RESET.SW_RES

T able 3. I2C ADDRESSES

Slave Address

I2C_ADDR

0 SCL1/SDA1 1 0 1 0 0 0 0 R/W 1 SCL1/SDA1 1 0 1 0 0 0 1 R/W 0 SCL2/SDA2 1 0 1 0 0 1 0 R/W 1 SCL2/SDA2 1 0 1 0 0 1 1 R/W

SCLx/SDAx

I2C Idle Mode

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Exiting I2C Idle Mode

The FUSB307B will exit I2C Idle mode when any I2C

Entering I2C Idle Mode

The FUSB307B does not need to enter I2C Idle Mode in

order to save power. Entering this mode has no effect on I

function. The FUSB307B can enter idle mode if 0xFF is written to the COMMAND register. Once in Idle mode, the

communication is addressed to the slave. The ALERTL.I_PRT_PWR interrupt will be set and no PWRSTAT bits will be set.

The device’s I

C block is always on without power

penalties.

FUSB307B will not set the PWRSTAT.TCPC_INIT to one.

www.onsemi.com

FUSB307B

VCONN Control

The FUSB307B integrates a CCx to VCONN switch with programmable OCP capability via the VCONN_OCP register. If PWRCTRL.VCONN_PWR is set to 0, the standard VCONN current limit is used (210.5 mA). If PWRCTRL.VCONN_PWR is set to 1, the programmable VCONN_OCP is used.

The VCONN switch can be enabled via the PWRCTRL register bits EN_VCONN and TCPC_CTRL.ORIENT bits (for CC1/2 selection).

A VCONN valid voltage is monitored and reported on PWRSTAT.VCONN_VAL. The valid voltage threshold is fixed at 2.4 V.

Debug Accessory Support

The FUSB307B implements autonomous detection of Source and Sink debug accessories. A debug accessory detection is indicated via a standard output. The FUSB307B powers on looking for a debug accessories without processor intervention. If debug accessory detection is not wanted, the processor can write TCPC_CTRL.DEBUG_ACC_CTRL = 1b.

Type−C Manual Mode Detection

The CC pull up (Rp) or pull down (Rd) resistors and DRP toggle are setup via the ROLECTRL register.If a TCPM wishes to control Rp/Rd directly, it can write ROLECTRL.DRP = 0b and the desired ROLECTRL bits [3:0] (CC1/CC2).

The FUSB307B can autonomously toggle the Rp/Rd by setting ROLECTRL.DRP = 1b and the starting value of Rp/Rd in ROLECTRL.bits [3:0]. DRP toggling starts by writing to the COMMAND register

If ROLECTRL.DRP = 1b, the only allowed values for CC1/CC2 in ROLECTRL bits [3:0] are Rp/Rp or Rd/Rd.

When ROLECTRL bits 3:0 are set to Open and ROLECTRL.DRP = 0b, the PHY and CC comparators are powered down.

The FUSB307B updates the CCSTAT register on a Connect, Disconnect, a change in ROLECTRL.DRP or a change (tTCPCFilter debounced) on the CC1 or CC2 wire.

The TCPM reads CCSTAT upon detecting an interrupt and seeing the ALERTL.I_CCSTAT = 1. The FUSB307B indicates the DRP status, the DRP result, and the current CC status in this register.

The FUSB307B will set CCSTAT.LOOK4CON = 0b when it has stopped toggling as a DRP.

The TCPM reads the CCSTAT.LOOK4CON to determine if the FUSB307B is toggling Rp/Rd when operating as a DRP, it then reads CCSTAT.CON_RES to determine if the FUSB307B is presenting an Rp or Rd and read the CCSTAT.CC1_STAT and CCSTAT.CC2_STAT to determine the CC1 and CC2 states.

The FUSB307B debounces the CC lines for tTCPCfilter before reporting the status on CCSTAT. The TCPM must complete the debounce as defined in T ype−C Specification.

www.onsemi.com

TCPM

Set FUSB305B to DRP

Write:

ROLECTRL.DRP = 1b ROLECTRL.CC2 = 01b or 10b ROLECTRL.CC1 = 01b or10b

ROLECTRL.CC1 = ROLECTRL.CC2

PWRCTRL.AUTO_DISCH = 0b

COMMAND.LOOK4CON

No Connection

Monitor for

Alert

FUSB307B

Connection

FUSB307B

DRP T oggling

Set CCSTAT.LOOK4CON = 1b

DrpToggleFlag = 1b

Start DRP Toggling

Monitor for a Connection

Service other

ALERTS

Read ALERT

ALERT.CCSTAT = 1b?

CCSTAT.LOOK4CON = 0b?

Read CCSTAT and debounce for

Yes

Read CCSTAT

Yes

Debounce CC Status

tCCDebounce

Potential Connect As Source

Either CC = Src.Rd or Both CC = Src.Ra

for > tTCPCFilter

Set Source Status

CCSTAT.LOOK4CON = 0b

CCSTAT.CON_RES = 0b

Stop T oggling Rp/Rd

Apply Rp

ALERT.CCSTAT = 1b

Interrupt

Set

Potential Connect As Sink

Either CC != Snk.Open

for > tTCPCFilter

Set Sink Status

CCSTAT.LOOK4CON = 0b

CCSTAT.CON_RES = 1b

Stop T oggling Rp/Rd

Apply Rd

Determine CC & VCONN

ROLECTRL.CC1 & CC2 per decision

Set PWRCTRL.AUTO_DISCH

Write COMMAND to Source/Sink Vbus per decision

Check PWRSTAT.VBUS_VAL = 1b

Check PWRSTAT.VCONN_VAL = 1b

Write:

TCPC_CTRL.ORIENT

PWRCTRL.EN_VCONN

Enable VBUS and VCONN

Clear ALERT .CCST A T

Connection Established

Monitor for ALERT

Figure 8. DRP Initialization and Connection Detection

Monitor for a disconnect

www.onsemi.com

FUSB307B

BMC Power Delivery

The Type−C connector allows USB Power Delivery (PD) to be communicated over the connected CC pin between two ports. The communication method is the BMC Power Delivery protocol and is used for many different reasons with the Type−C connector. Possible uses are outlined below.

• Negotiating and controlling charging power levels

• Alternative Interfaces such as MHL, Display Port

• Vendor specific interfaces for use with custom docks or

accessories

• Role swap for dual−role ports that want to switch who

is the host or device

• Communication with USB3.1 full featured cables

The FUSB307B integrates a thin BMC PD client which includes the BMC physical layer and packet buffers which allows packets to be sent and received by the host software through I

Receive State Machine

received by the FUSB307B via the RXDETECT register. This register defaults to 0x00 (Receiver disabled) upon power up, reset, Hard Reset transmission and reception, and upon detecting a cable disconnect. A message is not received unless it is first enabled. Figure 9 shows the FUSB307B receive state machine.

RXSTAT register is updated with the type of message

C accesses.

The TCPM can setup the desired types of messages to be

Upon a successfully transmitting GoodCRC, the

received and the TCPM is alerted via ALERTL.I_RXSTAT bit (see transition from PRL_Rx_Send_GoodCRC to PRL_Rx_Report_SOP* in Figure 9). The total number of bytes in the receive buffer RXDATA is stored in RXBYTECNT This number includes the header bytes that are stored in RXHEADL and RXHEADH and the RXSTAT register.

The RXBYTECNT, RXSTAT registers and the internal receive buffer will be cleared after the ALER TL.I_RXSTAT bit is cleared.

The FUSB307B will automatically transmit a GoodCRC message for valid enabled messages within tTransmit.

A received message is valid when:

• It is not a GoodCRC message

• The calculated CRC is correct

• The SOP* type is enabled

The makeup of the GoodCRC message is formed by the received SOP* type and the contents of MSGHEADR register.

When an expected GoodCRC message or a Hard Reset signaling is received, they will not be replied with a GoodCRC message (see Note 2 in Figure 9). If a GoodCRC message received was not expected due to the SOP* type or mismatched Message ID, the receive state machine will not send a GoodCRC message and will transition to PRL_Rx_Report SOP* to inform the TCPM.

If a Hard Reset message is received, the FUSB307B will reset the RXDETECT preventing the reception of future messages until the TCPM re−enables it.

Start

PRL_Rx_Wait_for_PHY_

Actions on entry:

1. This indication is sent by the PHY when a message has been discarded due to CC being busy, and after CC becomes idle again (see USB PD Spec).

2. Messages do not include Hard Reset or Cable Reset signals or expected GoodCRC messages (GoodCRC messages are only expected after the FUSB305 PHY has received the tx message and the FUSB305 Tx state−machine is in the PRL_Tx_Wait_for_PHY_response state).

FUSB305 receives Hard reset | Cable reset

message

PRL_Rx_Report_SOP*

Actions on entry: Update RECEIVE_STATUS

(ALERT_L.RXSTAT asserted)

Message received from PHY

(Note 1)

Message discarded

bus Idle (Note 2)

GoodCRC Transmission complete

Unexpected

GoodCRC received

PRL_Rx_Message_Discard

Actions on entry: If Tx State−Machine active, discard

transmission and assert ALERT_L.TXDISC

else

PRL_Rx_Send_GoodCRC

Actions on entry:

Send GoodCRC message to PHY

Figure 9. Receive State Machine

www.onsemi.com

FUSB307B

Transmit State Machine

To transmit a message, the TCPM must first write the entire message in the following registers: TXHEADL, TXHEADH, TXBYTECNT and the TXDATA.

The actual transmission starts when the TCPM writes the TRANSMIT register.

The TRANSMIT register is where the message selection is done and it must be written once per transmission.

The TRANSMIT and TXBYTECNT will be reset after executing a successful or failed transmission.

If the TRANSMIT.RETRY_CNT is set to a number greater than 0, the FUSB307B will automatically retry sending the same message if a GoodCRC is not received

ProtocolTransmit

Protocol Layer message reception

in PRL_Rx_Message_Discard state

PRL_Tx_Wait_for_ Message_Request

Actions on entry:

Reset RetryCounter.

PRL_Tx_Transmission_Error

Actions on entry:

Set ALERTL.I_TXFAIL interrupt

TRANSMIT[2:0] < 101b written

RetryCounter > NRETRIES

PRL_Tx_Check_RetryCounter

Actions on entry: If DFP or UFP,Increment and check

RetryCounter

(RXHEADH[3:1] != TXHEADH[3:1] (MessageID mismatch) |

TRANSMIT[2:0] != RXSTAT[2:0] (SOP mismatch) )

within tCRCReceiveTimer. An automatic retry is not performed when sending Hard−Resets, Cable−Resets, or BIST Carrier Mode 2 signaling.

The TCPM must not write the TRANSMIT register again until ALERTL.I_TXSUCC, I_TXFAIL, I_TX_DISC have been asserted and cleared.

The TCPM will not write the TRANSMIT register to request a transmission other than a Hard reset until it has cleared all received message alerts. If a TRANSMIT is written when ALERTL.I_RXSTAT = 1 or ALERTL. I_RXHRDRST = 1, the transmit request is discarded and ALERTL.I_TX_DISC is asserted.

PRL_Tx_Construct_Message

Actions on entry: Pass TXBYTECNT bytes from

TXHEADL and TXHEADH and

RetryCounter ≤

(Collision detected and now bus idle)

I_TX_MSG_DISC && bus idle

NRETRIES

(Note 4)

CRCReceiveTimer

Timeout

TXDATA to PHY

Message sent to PHY

PRL_Tx_Wait_for_PHY_response Actions on entry: Initialize and run CRCReceiveTimer

(Note 3)

GoodCRC response from

PHY layer

PRL_Tx_Message_Sent

Actions on entry:

Set ALERTL.I_TXSUCC

GoodCRC with MessageID and SOP match

PRL_Tx_Match_MessageID

Actions on entry: Match Extracted MessageID and

response MessageID

3. The CRCReceiveTimer is only started after the FUSB305 has sent the message. If the message is not sent due to a busy channel then the CRCReceiveTimer will not be started.

4. This Indication is sent by the PHY layer when a message has been discarded due to CC being busy, and after CC becomes idle again. The CRCReceiveTimer is not running in this case since no message has been sent.

Figure 10. Receive State Machine

www.onsemi.com

FUSB307B

Hard Reset/ Cable Reset State Machine

The TCPM will write the TRANSMIT register to initiate the Hard Reset/Cable Reset state machine, see Figure 11. If a the FUSB307B is in the middle of a transmission when instructed to send a Hard or Cable reset, it will set the ALERTL.I_TXDISC bit and send the hard reset signaling as soon as possible. The FUSB307B implements the HardResetCompleteTimer. A Hard Reset or Cable Reset

PRL_HR_Wait_for_Hard_Reset_

Request

Actions on entry:

PRL_HR_Report

Actions on entry: Assert ALERT.I_TX_SUCC and ALERT.I_TX_FAIL

Figure 11. Hard Reset and Cable Reset State Machine

TRANSMIT[2:0]=101b or 110b

written

PRL_HR_Failure

Actions on entry: Instruct PHY to stop attempting to

send Hard Reset or Cable Reset.

will be attempted until the HardResetCompleteTimer times out. After a successful transmission or timeout, the FUSB307B will indicate that a Hard Reset or Cable Reset has been sent by asserting both ALERTL.I_TXSUCC and ALERTL.I_TXFAIL registers simultaneously. The bits in RXDETECT and RXBYTECNT will be reset to disable PD message passing after a Hard Reset is received or transmitted.

PRL_HR_Construct_Message

Actions on entry:

Start tHardResetComplete timer Request PHY to send Hard Reset or

tHardResetComplete

expires

Actions on entry: Stop tHardResetComplete timer

Cable Reset

Hard Reset or Cable Reset sent

PRL_HR_Success

Automatic GoodCRC Response

Power Delivery packets require a GoodCRC acknowledge packet to be sent for each received packet where the calculated CRC is the correct value. This calculation is done by the FUSB307B.

The FUSB307B will automatically send the GoodCRC control packet in response to alleviate the local processor from responding quickly to the received packet. Once the GoodCRC packet is sent the FUSB307B will trigger the ALERTL.I_RXSTAT interrupt.

The following sequence of events occur internally within the FUSB307B without processor intervention when it is determined that the receive message has the correct CRC. If the host processor attempts a packet transmission during an Automatic GoodCRC response, the FUSB307B will set the ALERTL.I_TXDISC bit interrupting the processor. The processor should only transmit a new packet once ALERTL.I_TXSUCC or ALERTL.I_TX_FAIL has been received.

It is assumed that the processor will set the PWRCTRL.ORIENT to specify which channel USB−PD traffic will be transmitted or received.

BIST Mode

Bist Transmit

The FUSB307B will transmit Bist Carrier Mode 2 signaling when directed by the TCPM via TRANSMIT register. The FUSB307B will exit Bist Mode after tBISTContMode timer expires.

Bist Receive

When the FUSB307B is in Bist receive mode via TCPC_CTRL register, it will acknowledge these packets with a GoodCRC and automatically flush the buffer to allow for thousands of packets to be received without filling the receive buffer. Bist Receive mode will exit on a cable disconnect or a Hard Reset received.

VBUS Source and Sink Control

The FUSB307B can control a source and sink path via two outputs: SRC for the source path and SNK for the sink VBUS path.

These two outputs are controlled via the COMMAND register.

The SNK and SRC outputs will autonomously disable upon a cable detach.

www.onsemi.com

Voltage Transitions

The FUSB307B device can control a vSafe5V path via its

SRC output.

Transition to vSafe5v Path on Power up

FUSB307B

Service other

ALERTS

TCPM

Power Up

Prepare device to source vSafe5v

PWRCTRL.DIS_VALARM = 1b PWRCTRL.AUTO_DISCH = 0b

Write COMMAND.SourceVbusDefaultVoltage

Write:

Enable vSafe5v Source

Read

ALERT

ALERT.I_PORT_PWR=1b?

FUSB307B

Sourcing Disabled

PWRSTAT.SOURCE_VBUS = 0b

PWRSTAT.SOURCE_HV = 0b

SRC = Low

SRC_HV = Low

Enable SRC path

SRC = High

VBUS > vSafe5V(min)?

Voltage T ransition Complete

Set PWRSTAT.SOURCE_VBUS =1b

Set ALERT.I_PORT_PWR = 1b

Yes

Read ALERT

Read PWRSTAT

Enable Auto Discharge

PWRCTRL.AUTO_DISCH = 1b

Notify Policy Engine that voltage

transition is complete

Figure 12. Transition to vSafe5V on Power Up

Sourcing vSafe5V

www.onsemi.com

FUSB307B

Transition to HV using SRC enabled Path

Service other

ALERTS

TCPM

Accepted High Voltage

Policy Engine requests for VBUS transition

Enable external source path or transition existing

to high voltage

Enable Monitoring of VBUS

PWRCTRL.AUTO_DISCH = 0b PWRCTRL.DIS_VALARM = 0b

VALARMHCFG = vNewSrc (Min)

Write:

Transition HV Source

Source to HV

Read

ALERT

ALERT.I_VALARM_HI = 1b?

FUSB307B

Sourcing vSafe5V

PWRSTAT.SOURCE_VBUS = 1b

PWRSTAT.SOURCE_HV = 0b (if 307/8)

Set ALERTL.I_VBUS_ALARM_HI

SRC = High

Enable Monitoring of VBUS

SRC = High

Monitor VALARMHCFG

VALARMH Trip?

Yes

Read ALERT

Setup FUSB305 for HV Sourcing

Write:

VALARML/HCFG

PWRCTRL.AUTO_DISCH = 1b

Notify Policy Engine that voltage

transition is complete

Sourcing HV via SRC

NOTE: Transitioning from HV on SRC to vSafe5v also on SRC can be done by using Voltage Alarm Low. Power supply

is responsible for transitioning voltages to meet USB PD spec− no discharge necessary.

Figure 13. Transition to vSafe5V on Power Up

www.onsemi.com

FUSB307B

VBUS Monitoring and Measurement

The FUSB307B can monitor the presence of VBUS and will report it on PWRSTAT.VBUS_VAL and interrupt ALERT.I_PORT_PWR.

VBUS_VAL is set according to VBUS thresholds in vVBUSthr.

The FUSB307B also supports a more precise voltage measurement via an on−board ADC. The voltage on VBUS is measured at a rate of tVBUSsample and it is reported on VBUS_VOLTAGE_L/H register. The precision of the measurement is +/2% with a resolution of 25 mV LSB.

In addition to providing the μProcessor an accurate measurement of VBUS, the measurement in VBUS_VOLTAGE will be used when monitoring various user defined thresholds:

• Voltage alarms in registers VALARMLCFG and

VALARMHCFGL

• VBUS Disconnect Threshold in registers

VBUS_SNK_DISCL and VBUS_SNK_DISCH

• VBUS Stop Discharge Threshold in registers

VBUS_STOP_DISCL and VBUS_STOP_DISCH

• The FUSB307B implements Low and High VBUS

Voltage Alarms that can be programmable via VALARMLCFG and VALARMHCFG respectively. If the High or the Low thresholds are crossed, the FUSB307B will signal an interrupt on ALERTL.I_VBUS_ALRM_HIor ALERTH.I_VBUS_ALRM_LO respectively. These alarms can be disabled by writing PWRCTRL.DIS_VALARM to one

ALERTL.I_PORT_PWR is asserted if the bit−wise AND of PWRSTAT and PWRSTAMSK results in any bits that have the value 1.

VBUS Discharge

Manual Discharge

There are two types of manual discharge circuits implemented: A bleed discharge for low current and a force discharge. The bleed discharge can be manually enabled by writing a one to register bit PWRCTRL.EN_BLEED_DISCH. When enabled, the bleed discharge provides a low current load on VBUS of 7 kΩ (max.) via RBLEED. The force discharge is used to quickly discharge VBUS to vSafe0V by applying a dynamic load to VBUS via RFULL_DISCH. The force discharge can be manually enabled by writing a one to register bit PWRCTRL.FORCE_DISCH. When RFULL_DISCH is applied, the maximum slew rate allowed for discharging VBUS does not exceed vSrcSlewNeg 30 mV/μs as it is specified in the USB−PD spec.

Automatic discharge bit PWRCTRL. AUTO_DISCH must be disabled before enabling force discharge.

Automatic Source Discharge after a Disconnect

Automatic discharge can be enabled by setting PWRCTRL. AUTO_DISCH register bit. When in Source mode the FUSB307B will fully discharge VBUS to vSafe5V (max.) within tSafe5V and to vSafe0V within tSafe0V when a Disconnect occurs. The FUSB307B is in Source mode when the SRC output is asserted.

The FUSB307B in Source mode will detect a Disconnect if the CCSTAT.CCx_STAT field for the monitored CC pin indicates SRC.Open and enable the FULL Discharge pull−down device. The monitored CC pin is specified by TCPC_CTRL.ORIENT.

VBUS

Cable Disconnect

(CCSTAT change)

tSafe5V

Apply R

Figure 14. VBUS Auto Discharge as Source

tSafe0V

www.onsemi.com

vSafe5V

vSafe0V

time

FUSB307B

Automatic Sink Discharge after a Disconnect

Automatic discharge can be enabled by setting PWRCTRL. AUTO_DISCH register bit. When in Sink mode the FUSB307B will fully discharge VBUS to vSafe5V (max.) within tSafe5V and to vSafe0V within tSafe0V when a disconnect occurs. The FUSB307B is in Sink mode any time MSGHEADR.POWER_ROLE = 0.

Whenever the system is sinking voltages greater than vSafe5V, a disconnect will be detected based on VBUS_SNK_DISC registers.

If the system is only sinking vSafe5V, a disconnect will be detected when VBUS_VAL goes low.

Due to the high capacitance on VBUS (up to 100

F) the FUSB307B may not immediately know if VBUS has been removed. The FUSB307B with Automatic Discharge on will apply RBLEED discharge load to VBUS until it crosses below VBUS_SNK_DISC.

The FUSB307B has to detect a disconnect within

tDisconnectDetect (6 ms) from VBUS crossing

VBUS

VBUS_SNK_DISCL. Once the FUSB307B has detected a Disconnect, RFULL_DISCH will be enabled bringing the VBUS voltage down to vSafe0V.

Whenever the FUSB307B detects a Disconnect, it will not

present Rd (or Rp) until VBUS reaches vSafe0V.

When the VBUS voltage goes below vSafe0V, the

auto−discharge circuit will disable.

If the discharge of VBUS to below vSafe0V is not accomplished by tSafe0V (650 ms), the FUSB307B will set the interrupt

NOTE: ALERTL.I_PORT_PWR is asserted if the

bit−wise AND of PWRSTAT and PWRSTAMSK results in any bits that have the value 1.

ALERTH. I_FAULT bit and the status FAULTSTAT.DISCH_FAIL. The discharge circuit is not turned off when this happens.

In tSinkDischargeBleed + tSinkDischargeFull have to be less than tSafe5V to comply with USB−PD spec.

VBUS_SNK_DISC

BLEED

Cable Disconnect

Figure 15. VBUS Auto Discharge as SinkSource

tDisconnectDetect

tSinkDischargeBleed

tSafe5V

Apply R

tSafe0V

FULL_DISCH

tSinkDischarge

Full

vSafe5V

vSafe0V

time

www.onsemi.com

FUSB307B

Discharge during a Connection

The discharge functions can be manually activated via the

PWRCTRL.FORCE_DISCH register. The discharge

VBUS

vSrcNew

VBUS_STOP_DISC

PWRCTRL.FORCE_DISCH

Apply R

FORCE

pull−down is specified by RFULL_DISCH. The FUSB307B will automatically disable discharge when VBUS reaches VBUS_STOP_DISC threshold

tSrcSettle

time

Figure 16. Sink Discharge during a Connection

Sink Discharge during a Connection

When the device is operating as a sink and it receives a Hard Reset or a Power Role Swap, the automatic discharge circuitry and SNK output will be disabled by the host processor to avoid a disconnect detection.

Watchdog Timer

The watchdog timer functionality is enabled whenever TCPC_CTRL.EN_WA TCHDOG i s set to 1b. The watchdog timer should only be enabled after an attach when the device is in Attached.Src, Attached.Snk or Apply.ROLECONTROL states. The watchdog timer starts

when any of the interrupts that are not masked in the Alert register are set or when the INTB pin is asserted. The watchdog timer is cleared on an I2C access by the TCPM (either read or write). If the INTB pin is still asserted after this I2C access, the watchdog timer will reinitialize and start monitoring again until all of the Alerts are cleared or until the INTB pin is de−asserted.

When the watchdog timer expires, the FUSB307B will immediately disconnect the CC terminations by setting ROLE_CONTROL bits 3..0 to 1111b, disable all SRC/SRC_HV or SNK outputs, discharge VBUS to vSafe0V, and set FAULT_STATUS.I2CInterfaceError.

www.onsemi.com

FUSB307B

USB−PD Rev 3.0 Features

The Sink TCPM that desires to transmit will write the TX Buffers and SINK_TRANSMIT register. The FUSB307B

Extended Data Messages

Extended Data Messages is only supported via Chunking where large messages are broken into 2 or more 26 byte chunks.

SinkTx

The USB−PD Rev 3.0 has added this feature to allow the Sink to safely transmit a message reducing the risk of collisions.

The Protocol layer in the Source will request to set the Rp value to SinkTxOk to indicate that the Sink can initiate an Atomic Message Sequence (AMS). The Protocol layer in the Source will request to set the Rp value to SinkTxNG to indicate that the Sink cannot initiate an AMS since the Source is about to initiate an AMS.

Table 4. RP SETTINGS FOR SINK TX

Source Rp Parameter Description Sink Operation Source Operation

1.5 A @5 V SinkTxNG Sink Transmit “No Go”

3.0 A @5 V SinkTxOk Sink Transmit “OK” Sink can initiate an AMS Source cannot initiate an AMS

5. The TCPM is responsible for tSinkTx timer.

will wait for the Rp value to be set to SinkTxOk before transmitting the message. If Rp is already set to SinkTxOk, a SINK_TRANSMIT will transmit immediately.

In the case where the Sink TCPM wants to abort the message transmission before the Rp value has changed to SinkTxOk, it can write SINK_TRANSMIT.EN_SNK_TX = 0b. If a transmission has already started, writing this register will be ignored and a FAULTSTAT.I2C_ERR interrupt will be generated.

If TXBYTECNT is less than 2h when a SINK_TRANSMIT.TXSOP <101 is requested, a FAULTSTAT.I2CERR interrupt is generated.

The ALERTL.I_RXSTAT must be cleared when SINK_TRANSMIT is written or an ALERTL.I_TX_DISC is asserted.

Sink cannot initiate an AMS.

Sink can only respond to

Messages as part of an AMS

Source can initiate an AMS

tSinkTx after setting Rp to this

value (Note 5)

while this value is set

Fast Role Swap

Fast Role Swap is the process of exchanging the Source and Sink roles between Port Partners rapidly due to the disconnection of an external power supply.

The Fast Role Swap process is intended for use by a PDUSB HUB that presently has an external wall supply, and is providing power both through its downstream Ports to USB Devices and upstream to a USB Host such as a notebook. On removal of the external wall supply Fast Role Swap enables a VBUS supply to be maintained by allowing the USB Host to apply vSafe5V after having detected Fast Role Swap signaling.

The initial Source will signal a Fast Role Swap request by driving CC to ground with a resistance of less than

rFRSwapTx for tFRSwapTx. The initial Source shall only signal a Fast Role Swap when it has an Explicit Contract. On transmission of the Fast Role Swap signal any pending Messages will be Discarded by internally toggling PD_RESET. The Fast Role Swap signal may override any active transmissions. Since the initial Sink’s response to th e Fast Role Swap signal is to send a FR_Swap Message, the initial Source shall ensure Rp is set to SinkTxOk once the Fast Role Swap signal is complete.

The flow diagram in Figure 17 demonstrates the HUB and Host function during the initial Fast Role Swap process. The AMS and Power Role swap necessary to complete the Fast Role Swap is performed by the respective TCPMs.

www.onsemi.com

+ 39 hidden pages