ON Semiconductor FST3125 User Manual

FST3125

4-Bit Bus Switch

The ON Semiconductor FST3125 is a quad, high performance switch. The device is CMOS TTL compatible when operating between 4 and 5.5 Volts. The device exhibits extremely low R nearly zero propagation delay. The device adds no noise or ground bounce to the system.

The device consists of four independent 1−bit switches with separate Output/Enable (OE OE

is low. If OE is high, the switch is high Z.

) pins. Port A is connected to Port B when

and adds

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MARKING

DIAGRAMS

Features

• R

t 4 W Typical

• Less Than 0.25 ns−Max Delay Through Switch

• Nearly Zero Standby Current

• No Circuit Bounce

• Control Inputs are TTL/CMOS Compatible

• Pin−For−Pin Compatible With QS3125, FST3125, CBT3125

• All Popular Packages: TSSOP−14, SOIC−14

• These are Pb−Free Devices

GND

Figure 1. Pin Assignment for

SOIC and TSSOP

14 13 12 11 10

4A 4B OE

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb−Free Package

(Note: Microdot may be in either location)

FST3125G

AWLYWW

FST

3125

ALYWG

PIN NAMES

OE1, OE2, OE3, OE

1A, 2A, 3A, 4A

1B, 2B, 3B, 4B Bus B

NC Not Connected

Description

Bus Switch Enables

Bus A

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

June, 2013 − Rev. 0

1 Publication Order Number:

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

FST3125/D

FST3125

TRUTH TABLE

Inputs Outputs

OE A, B

Figure 2. Logic Diagram

L A = B

H Z

ORDERING INFORMATION

Device Order Number Package Shipping

FST3125DR2G SOIC−14

(Pb−Free)

FST3125DTR2G TSSOP−14

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

2500 Units / Tape & Reel

†

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FST3125

MAXIMUM RATINGS

Symbol Parameter Value Unit

GND

STG

MSL Moisture Sensitivity Level 1

ESD

Latchup

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.

2. Tested to EIA/JESD22−A114−A.

3. Tested to EIA/JESD22−A115−A.

4. Tested to EIA/JESD78.

DC Supply Voltage *0.5 to )7.0 V

DC Input Voltage *0.5 to )7.0 V

DC Output Voltage *0.5 to )7.0 V

DC Input Diode Current VI t GND *50 mA

DC Output Diode Current VO t GND *50 mA

DC Output Sink Current 128 mA

DC Supply Current per Supply Pin $100 mA

DC Ground Current per Ground Pin $100 mA

Storage Temperature Range *65 to )150

Lead Temperature, 1 mm from Case for 10 Seconds 260

Junction Temperature Under Bias )150

Thermal Resistance (Note 1) SOIC

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

TSSOP

ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

Charged Device Model

Latchup Performance Above VCC and Below GND at 85_C (Note 4)

125 170

u4000

u400

u2000

$100 mA

_C/W

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

Dt/DV

5. Unused control inputs may not be left open. All control inputs must be tied to a high− or low−logic input voltage level.

Supply Voltage Operating, Data Retention Only 4.0 5.5 V

Input Voltage (Note ) 0 5.5 V

Output Voltage (HIGH or LOW State) 0 5.5 V

Operating Free−Air Temperature −55 +125

Input Transition Rise or Fall Rate Switch Control Input

Switch I/O

0 0

ns/V

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FST3125

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Conditions (V) Min Typ* Max Unit

Clamp Diode Resistance IIN = *18mA 4.5 *1.2 V

High−Level Input Voltage 4.0 to 5.5 2.0 V

Low−Level Input Voltage 4.0 to 5.5 0.8 V

Input Leakage Current 0 v VIN v 5.5 V 5.5 $1.0

OFF−STATE Leakage Current 0 v A, B v V

Switch On Resistance (Note 6) VIN = 0 V, IIN = 64 mA 4.5 4 7

5.5 $1.0

VIN = 0 V, IIN = 30 mA 4.5 4 7

VIN = 2.4 V, IIN = 15 mA 4.5 8 15

VIN = 2.4 V, IIN = 15 mA 4.0 11 20

Quiescent Supply Current VIN = VCC or GND, I

Increase In ICC per Input One input at 3.4 V, Other inputs at VCC or GND 5.5 2.5 mA

= 0 5.5 3

OUT

*Typical values are at VCC = 5.0 V and TA = 25_C.

6. Measured by the voltage drop between A and B pins at the indicated current through the switch.

AC ELECTRICAL CHARACTERISTICS

VCC = 4.5 to 5.5 V VCC = 4.0 V

Symbol Parameter Conditions Figures Min Max Min Max Unit

PHL

PZH

PHZ

Prop Delay Bus to Bus (Note 7)

PLH

Output Enable Time VI = 7 V for t

PZL

Output Disable Time VI = 7 V for t

PLZ

7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the

typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).

VI = OPEN 3 and 4 0.25 0.25 ns

VI = OPEN for t

PZL

PLZ

PZH

PHZ

3 and 5 1.0 5.0 5.5 ns

3 and 5 1.5 5.3 5.6 ns

TA = −55_C to +125_C

Limits

TA = −55_C to +125_C

CAPACITANCE (Note 8)

Symbol Parameter Conditions Ty p Max Unit

Control Pin Input Capacitance VCC = 5.0 V 3 pF

Input/Output Capacitance VCC, OE = 5.0 V 5 pF

I/O

8. TA = )25_C, f = 1 MHz, Capacitance is characterized but not tested.

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FST3125

AC Loading and Waveforms

FROM

OUTPUT

UNDER

TEST

CL*

NOTES:

1. Input driven by 50 W source terminated in 50 W.

2. CL includes load and stray capacitance. = 50 pF

Figure 3. AC Test Circuit

= 2.5 nS

90 %

SWITCH INPUT

OUTPUT

90 %

10 % 10 %

PLH

1.5 V 1.5 V

500 W

= 2.5 nS

1.5 V1.5 V

Vmi

3.0 V

GND

PLH

ENABLE INPUT

= 2.5 nS

OUTPUT

Figure 4. Propagation Delays

90 %

1.5 V

10 %10 %

PZL

1.5 V

PZH

1.5 V

90 %

1.5 V

= 2.5 nS

PZL

PHZL

3.0 V

GND

+ 0.3 V

− 0.3 V

Figure 5. Enable/Disable Delays

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 1:1

SOIC−14 NB

CASE 751A−03

ISSUE L

DATE 03 FEB 2016

0.25 B

0.10

14X

0.58

13X

SOLDERING FOOTPRINT*

6.50

A B

0.25 B

SEATING

PLANE

14X

1.18

1.27 PITCH

DETAIL A

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

DETAIL A

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

DIM MIN MAX MIN MAX

A 1.35 1.75 0.054 0.068 A1 0.10 0.25 0.004 0.010 A3 0.19 0.25 0.008 0.010

b 0.35 0.49 0.014 0.019

D 8.55 8.75 0.337 0.344

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.019

L 0.40 1.25 0.016 0.049

M 0 7 0 7

__ __

INCHESMILLIMETERS

GENERIC

MARKING DIAGRAM*

XXXXXXXXXG

AWLYWW

XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42565B

SOIC−14 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2

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SOIC−14

CASE 751A−03

ISSUE L

DATE 03 FEB 2016

STYLE 1:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. NO CONNECTION

5. ANODE/CATHODE

6. NO CONNECTION

7. ANODE/CATHODE

8. ANODE/CATHODE

9. ANODE/CATHODE

10. NO CONNECTION

11. ANODE/CATHODE

12. ANODE/CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 5:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. ANODE/CATHODE

5. ANODE/CATHODE

6. NO CONNECTION

7. COMMON ANODE

8. COMMON CATHODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. ANODE/CATHODE

12. ANODE/CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 2:

CANCELLED

STYLE 6:

PIN 1. CATHODE

2. CATHODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

7. CATHODE

8. ANODE

9. ANODE

10. ANODE

11. ANODE

12. ANODE

13. ANODE

14. ANODE

STYLE 3:

PIN 1. NO CONNECTION

2. ANODE

3. ANODE

4. NO CONNECTION

5. ANODE

6. NO CONNECTION

7. ANODE

8. ANODE

9. ANODE

10. NO CONNECTION

11. ANODE

12. ANODE

13. NO CONNECTION

14. COMMON CATHODE

STYLE 7:

PIN 1. ANODE/CATHODE

2. COMMON ANODE

3. COMMON CATHODE

4. ANODE/CATHODE

5. ANODE/CATHODE

6. ANODE/CATHODE

7. ANODE/CATHODE

8. ANODE/CATHODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. COMMON CATHODE

12. COMMON ANODE

13. ANODE/CATHODE

14. ANODE/CATHODE

STYLE 4:

PIN 1. NO CONNECTION

2. CATHODE

3. CATHODE

4. NO CONNECTION

5. CATHODE

6. NO CONNECTION

7. CATHODE

8. CATHODE

9. CATHODE

10. NO CONNECTION

11. CATHODE

12. CATHODE

13. NO CONNECTION

14. COMMON ANODE

STYLE 8:

PIN 1. COMMON CATHODE

2. ANODE/CATHODE

3. ANODE/CATHODE

4. NO CONNECTION

5. ANODE/CATHODE

6. ANODE/CATHODE

7. COMMON ANODE

8. COMMON ANODE

9. ANODE/CATHODE

10. ANODE/CATHODE

11. NO CONNECTION

12. ANODE/CATHODE

13. ANODE/CATHODE

14. COMMON CATHODE

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42565B

SOIC−14 NB

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SCALE 2:1

0.10 (0.004)

SEATING

−T−

PLANE

U0.15 (0.006) T

2X L/2

PIN 1 IDENT.

U0.15 (0.006) T

SOLDERING FOOTPRINT

14X REFK

0.10 (0.004) V

−V−

7.06

TSSOP−14 WB

−U−

CASE 948G

ISSUE C

DETAIL E

SECTION N−N

DETAIL E

0.25 (0.010)

DATE 17 FEB 2016

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

INCHESMILLIMETERS

−W−

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

GENERIC

MARKING DIAGRAM*

XXXX XXXX

ALYWG

A = Assembly Location L = Wafer Lot Y = Year

0.65 PITCH

W = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

*This information is generic. Please refer to

14X

0.36

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

14X

1.26

98ASH70246A

TSSOP−14 WB

DIMENSIONS: MILLIMETERS

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

PAGE 1 OF 1

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ON Semiconductor FST3125 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual