28 V Rated OVLO/UVLO
Controller with Negative
Stress Protection
FPF2260ATMX
Description
FPF2260ATMX is an OVP and UVLO controller with reverse /
negative voltage protection. The device controls and drives a pair of
external N−MOSFET that can operate over an input voltage range of
2.8 V to 23 V. In that way, with OVP feature implemented, the system
can allow huge current as long as the external MOSFET can handle.
When the input voltage exceeds the over−voltage threshold or lower
than under−voltage threshold, the external FET is turned off
immediately to prevent damage to the protected downstream
components.
When the input voltage is stressed a negative voltage, the external
FET will also be turned off and prevent OUT dropping to negative
voltage.
FPF2260ATMX is available in a small X2QFN12 package and
operate over the free−air temperature range of −40°C to +85°C.
Features
• Over−voltage Protection Up to ±28V
• Programmable Over−voltage Lockout (OVLO)
♦ Externally Adjustable via OVLO Pin
♦ Default OVLO Level without Additional Components
• Programmable Under−voltage Lockout (UVLO)
♦ Externally Adjustable via UVLO Pin
• Active−high Enable Pin (EN) for Device
• Super−fast OVLO Response Time: Typical 150 ns
• Negative Voltage Blocking
• Short Circuit Protection and Auto−restart
• Selectable Gate Driver Voltage
• USB OTG Support Mode
• Open−Drain Output Indicators
♦ OVFLGB for Over Voltage Stress
♦ UVFLAG for Under Voltage Lockout
• Robust ESD Performance
♦ 2 kV Human Body Model (HBM)
♦ 1 kV Charged Device Model (CDM)
Typical Applications
• Mobile Phones
• PDAs
• Notebooks
• Desktops
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X2QFN12 1.6x1.6, 0.4P
CASE 722AG
MARKING DIAGRAM
1
6BKK
_XYZ
6B = Specific Device Code
KK = 2−Digits Lot Run Traceability Code
_ = Pin 1 Identifier
XY = 2−Digit Date Code
Z = Assembly Pant Code
PIN CONNECTIONS
UVLO
TRCBENGT_CON
12 11 10 9
GT2
81
72
OUT
OVFLGB
UVFLAG
GND
OVLO
3456
IN
GT1
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2020
July, 2020 − Rev. 3
1 Publication Order Number:
FPF2260ATMX/D
FPF2260ATMX
HV Battery
Charger
Travel
Adapter
USB Type C connector
Legacy USB
IN
VBUS
/
NTTFSC02N
GT1
IN
R1
UVLO
R2
OVLO
GT_CON
R3
NTTFSC02N
FPF2260A
TRCB
GT2
OUT
EN
OVFLGB
UVFLAG
GND
RPU
VIO
Figure 1. Schematic − Adjustable Option
Gate Driver, Charge Pump,
Bandgap, Oscillator
1 mF1 mF
Processor
RPU
VIO
OUT
GT1
GT2
UVLO
OVLO
UVLO
LOGIC
OVP
EN
GT_CON
TRCB
Figure 2. Simplified Block Diagram
OVFLGB
UVFLAG
GND
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2
FPF2260ATMX
PIN FUNCTION DESCRIPTION
Pin No. Name Description
1 GND Ground
2 OVLO OVLO Input: Over Voltage Lockout Adjustment Input
3 IN Power Input: External FET Input and Device Supply
4 GT1 Gate 1 Output:
5 GT2 Gate 2 Output:
6 OUT Power Output: External FET Output and Device Supply(More Description)
7 UVFLAG UVLO Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate no
8 OVFLGB OVP Flag Output: Open−drain output, turn ON the internal MOS to pull down this pin to indicate
9 EN
10 GT_CON
11 UVLO UVLO Input: Under Voltage Lockout Adjustment Input
12 TRCB
Under−Voltage condition on IN
Over−Voltage condition on IN
Enable Input: Active HIGH with internal 500 kW pull down resistor
Gate Voltage Control Input: VGS select Pin 0: Vgs = 12 V; 1/floating: Vgs = 6V with internal 500 kW
pull up resistor
True RCB Enable Input: 0: no TRCB; 1/floating: Block Reverse Current Entirely with internal 500 kW
pull up resistor
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
V
V
HVIO
T
J(max)
IN
OUT
I/O
Input Voltage Range (Note 1) −28 to +28 V
Output Voltage Range −0.3 to +28 V
Standard I/O Range (UVFLAG, OVFLGB, TRCB, GT_CON) −0.3 to +6 V
HV I/O Range (OVLO, UVLO, EN) −0.3 to +28 V
Maximum Junction Temperature 150 °C
TSTG Storage Temperature Range −65 to 150 °C
ESDHBM ESD Capability, Human Body Model (Note 2) ±2 kV
ESDCDM ESD Capability, Charged Device Model (Note 2) ±1 kV
T
SLD
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101)
Latch−up Current Maximum Rating: v150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Symbol Rating Value Unit
R
q
JA
Thermal Characteristics, X2QFN12 (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
4. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
5. Values based on 2S2P JEDEC std. PCB.
139.3 °C/W
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3
FPF2260ATMX
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
in
Supply Voltage on VIN (GT_CON floating)
Supply Voltage on VIN (GT_CON grounded) 16
V
OVLO, UVLO, EN,
TRCB, GT_CON,
OVFLAG, UVFLAG
C
in
C
out
T
A
I/O pins 0 5.5 V
IN Capacitor 1 −
OUT Capacitor 1 −
Ambient Temperature −40 85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4.0
22
V
mF
mF
ELECTRICAL CHARACTERISTICS (V
I
≤ 3 A, CIN = 0.1 mF, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6)
IN
Symbol
Parameter Test Condition Min Typ Max Unit
= 2.9 to 23 V, CIN = 0.1 mF, C
IN
= 0.1 mF, TA = −40 to 85°C; For typical values VIN = 5.0 V,
OUT
LEAKAGE AND QUIESCENT CURRENTS
I
I
OFF
I
IN_Q
I
OVLO
Input Quiescent Current on VIN
Q
VIN = 5 V, V
V
OUT
VIN = 20 V, V
V
OUT
Device turned off current VIN = 5 V, VEN = 0 V, V
Supply Current during Over Voltage VIN = 20 V, V
OVLO Input Leakage Current V
OVLO
floating
floating
= V
OVLO_TH
= 1 V, TRCB = 0,
OVLO
= 1 V, TRCB = 0,
OVLO
= 1.8 V, V
OVLO
= 0 V − 120 −
OUT
= 0 V − 180 −
OUT
OVER VOLTAGE AND UNDER VOLTAGE LOCKOUT
V
DEF_OVLO
V
DEF_UVLO
V
OVLO_TH
V
HYS_OVLO
V
UVLO_TH
V
HYS_UVLO
V
OV_RNG
Default Over−Voltage Trip Level VIN rising, TA = −40 to 85°C 5.9 6.1 6.3 V
Default Under−Voltage Trip Level VIN falling, TA = −40 to 85°C 1.8 2.0 2.2 V
OVLO set threshold V
rising from 1.1 V to 1.3 V, the OVLO
OVLO
voltage to switch off power FET
OVLO threshold hysteresis − 2 − %
UVLO set threshold V
falling from 1.3 V to 1.1 V, the UVLO
UVLO
voltage to switch off power FET
UVLO threshold hysteresis − 2 − %
Adjustable OVLO range V
> 0.5 V 4 − 22 V
OVLO
TRCB (IN TRCB MODE ONLY, I.E. VTRCB = HIGH/FLOAT)
V
t
DROP
REL
TRCB trigger level VIN = 5 V, I
TRCB release time VIN = 5 V − 1 − ms
= 100 mA − 35 − mV
LOAD
I/O THRESHOLDS
OVLO Input Threshold Voltage
V
IH_OVLO
V
IL_OVLO
Voltage Increasing, Logic High
Voltage Decreasing, Logic Low
High
Low
GATE DRIVER
V
I
GS
Turn on status gate positive voltage over
GS
OUT
(Note 8)
Turn on status gate positive current V
OVP turn off gate current (Note 9) VIN = 5 V, V
VIN = V
VIN = V
TRCB
V
GT_CON
to 1.3 V
= 5 V, V
OUT
= 5 V, V
OUT
= 0 V, VIN = V
= 1.8 V, I
LOAD
GT_CON
= 0 V − 12 −
GT_CON
= 1.8 V − 6 −
GT_CON
= 5 V,
OUT
= 10 mA
= 1.8 V, V
OVLO
from 1.1 V
− 160 − mA
− 400 −
mA
mA
−100 − 100 nA
1.15 1.19 1.23 V
1.15 1.17 1.23 V
0.3
−
−
− 0.15VV
− − 10
mA
− − 3 A
V
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4
FPF2260ATMX
ELECTRICAL CHARACTERISTICS (V
I
≤ 3 A, CIN = 0.1 mF, TA = 25°C, for min/max values TA = −40°C to 85°C; unless otherwise noted. (Note 6) (continued)
IN
= 2.9 to 23 V, CIN = 0.1 mF, C
IN
= 0.1 mF, TA = −40 to 85°C; For typical values VIN = 5.0 V,
OUT
Symbol UnitMaxTypMinTest ConditionParameter
I/O AND LOGIC CONTROL
V
V
V
I
LKG
I/O Logic High Voltage
IH
I/O Logic Low Voltage − − 0.5 V
IL
Output Low Voltage of Open−Drain pins V
OL
Leakage Current of I/O pins V
Pins: EN, TRCB, GT_CON
= 3.3 V, I
I/O
Pins: UVFLAG, OVFLGB
= 3.3 V, Logic de−asserted,
I/O
Pins: UVFLAG, OVFLGB, GT_CON
SINK
= 1 mA,
1.2 − − V
− − 0.4 V
−0.5 − 0.5
mA
TIMING
t
SW_DEB
t
OTG_DEB
t
UV_DEB
t
OV_DEB
t
t
OFF
De−bounce Time of Power FET turned on Time from 2.5 V < VIN < V
V
= 0.1 x V
OUT
De−bounce Time of OTG turned on Time from V
De−bounce Time of UVFLAG flag Time from VIN > V
De−bounce Time of OVFLGB flag Time from VIN < V
Switch Turn−On rising Time (Note 9)
R
Switch Turn−Off Time (Note 8, 9)
VIN = 5 V, RL = 100 W, CL = 22 mF, V
0.1 x V
IN
RL = 10 W, CL = 0 μF, time from VIN > V
to V
OUT
Internal OVP level
External OVP level (Note 10)
IN
> 2.8 V to VIN = 0.1 x V
OUT
IN_UVLO
IN_OVLO
to 0.9 x V
= 0.9 x V
IN
IN
IN_OVLO
to
OUT
− 15 − ms
− 15 − ms
to UVFLAG < 0.4 V − 130 −
to OVFLGB > 1.8 V − 1 − ms
OUT
from
OVLO
− 2 − ms
−
−50100−−
ns
ns
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
= TA = 25°C. Low
J
7. Refer to the APPLICATION INFORMATION section.
8. Based on the recommended MOSFET devices.
9. Values based on design and/or characterization
10.Depends on the capacitance on OVLO pin.
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5
FPF2260ATMX
TYPICAL CHARACTERISTICS
Figure 3. Quiescent Current over Temperature Figure 4. Quiescent Current over V
Figure 5. Power−Up Transient
(V
= 5 V, C
IN
OUT
= 0.1 mF)
Figure 6. Power−Down Transient
(V
= 5 V, C
IN
OUT
= 0.1 mF)
IN
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6
FPF2260ATMX
†
FUNCTION DESCRIPTION
General
FPF2260A is an OVP controller to drive external N−type
MOSFETs. The device can protect next stage system which
is optimized to lower voltage working condition, especially
with ultra−high charging current. The device includes
multi−functions including OVP, Advanced TRCB, and
Negative Stress protection.
Power MOSFET Driver
The FPF2260A integrates charge pump driver to control
external N−type MOSFET pair. The drive voltage can be
configured by GPIO for different MOSFET.
The drive voltage for MOSFET can be configured by
GPIO pin GT_CON. V
GT_CON to high or floating. Or, V
could be set to 6 V by pull
GS
will be set to 12 V by
GS
pulling GT_CON to ground.
True Reverse Current Blocking and USB OTG
The FPF2260A support advanced TRCB mode by pulling
TRCB pin to high or floating it. In the advanced TRCB
mode, no reverse current will be seen from OUT to IN
through the external MOSFETs if V
– VIN > 30 mV.
OUT
When advanced TRCB mode is active, OTG operation is
not supported. If OTG is needed, TRCB pin needs to be
pulled down to ground.
Enable Control
The GPIO EN is an active high control pin. When the
voltage is pulled low, FPF2260A will disable the external
MOSFETs by connecting GT1 to IN and GT2 to OUT.
When EN is logic high, FPF2260A will close external
MOSFET if there are no over stressed condition.
Under Voltage Lockout
FPF2260A will turn the FETs off when the voltage on IN
is lower than the UVLO threshold V
IN_UVLO
.
Whenever IN voltage ramps up to higher than the
threshold, the power FET will be turned on automatically
after t
de−bounce time if there is no other over stressed
DEB
condition.
The external resistor ladder can be decided according to
the following equation:
V
IN_UVLO
+ V
[1 ) R1 ń (R2 ) R3)]
UVLO_TH
(eq. 1)
where R1, R2 and R3 are the resistors in figure 1.
Over Voltage Lockout
The power FET will be turned off whenever IN voltage
higher than V
IN_OVLO
external resistor ladder or just be default value V
When V
When V
once V
OVLO
> 0.3 V, the power switch will be turned off
OVLO
> V
OVLO
. The value of V
≤ 0.3 V, V
OVLO_TH
IN_OVLO
is decided by default value.
OVLO
can be set by
IN_OVLO
. The external resistor ladder can
be decided according to the following equation:
V
IN_OVLO
+ V
[1 ) (R1 ) R2) ń R3]
OVLO_TH
(eq. 2)
where R1, R2 and R3 are the resistors in figure 1.
Negative Voltage Protection
FPF2260 support negative voltage protection to help
system avoid unexpected negative stress. The gate of first
external power FET, GT1, will be pulled down with the
voltage on IN when it is negative. This behavior can keep the
external FET at off status till −28 V.
APPLICATIONS INFORMATION
Input Decoupling (Cin)
A ceramic or tantalum at least 0.1 mF capacitor is
recommended and should be put before and close the
connection point of MOSFET and FPF2260A IN. Higher
capacitance and lower ESR will improve the overall line and
load transient response.
Output Decoupling (C
out
)
The FPF2260A is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. The minimum output decoupling value is
0.1 mF and can be augmented to fulfill stringent load
transient requirements.
Hints for PCB Layout
The external MOSFET is an important part to FPF2260A.
The connection of gate should be as short as possible to
avoid parasitic resistance and inductance for better OVP
performance.
.
ORDERING INFORMATION
Part Number Marking Package Shipping
FPF2260ATMX 6B X2QFN12 5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2QFN12 1.6x1.6, 0.4P
CASE 722AG
ISSUE A
DATE 26 SEP 2017
DOCUMENT NUMBER:
DESCRIPTION:
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98AON13772G
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